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| ? s14058 LSI53C825A/825ae pci to scsi i/o processor technical manual january 2001 version 3.1
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?cer of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?cer is prohibited. document db14-000159-00, fourth edition (january 2001) this document describes the lsi logic LSI53C825A/ae pci to scsi i/o processor and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1998C2001 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, tolerant, sdms, and scripts are registered trademarks or trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. preface iii preface this book is the primary reference and technical manual for the lsi logic LSI53C825A/825ae pci to scsi i/o processor. it contains a complete functional description for the LSI53C825A/825ae and includes complete physical and electrical speci?cations for the LSI53C825A/825ae. audience this technical manual is intended for system designers and programmers who are using this device to design a scsi port for pci-based personal computers, workstations, or embedded applications. organization this document has the following chapters and appendixes: chapter 1, introduction , includes general information about the LSI53C825A and other members of the lsi53c8xx family of pci to scsi i/o processors. chapter 2, functional description , describes the main functional areas of the chip in more detail, including the interfaces to the scsi bus. chapter 3, signal descriptions , describes the chips connection to the pci bus, including the pci commands and con?guration registers supported. chapter 4, registers , contains the pin diagrams and de?nitions of each signal. chapter 5, scsi scripts instruction set , describes each bit in the operating registers, organized by address. iv preface chapter 6, speci?cations , de?nes all of the scsi scripts instructions that are supported by the LSI53C825A. appendix a, register summary , contains a register summary. appendix b, external memory interface diagram examples , contains several example interface drawings to connect the LSI53C825A to an external rom. related publications for background information, please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2); x3.253 ( scsi-3 parallel interface ) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface lsi logic world wide web home page www.lsilogic.com preface v scsi scripts? processors programming guide , version 2.2, order number s15044.a pci special interest group 2575 n. e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the pre?x 0x for example, 0x32cf. binary numbers are indicated by the pre?x 0b for example, 0b0011.0010.1100.1111. revision record revision date remarks 1.0 6/95 revision 1.0 2.0 3/96 revision 2.0 3.0 12/97 revision 3.0 3.1 1/01 product names changed from sym to lsi. vi preface contents vii contents chapter 1 introduction 1.1 general description 1-1 1.2 package and feature options 1-2 1.2.1 pci pad power-up sequence 1-3 1.3 tolerant ? technology 1-3 1.4 LSI53C825A bene?ts summary 1-4 1.4.1 scsi performance 1-4 1.4.2 pci performance 1-5 1.4.3 integration 1-6 1.4.4 ease of use 1-6 1.4.5 flexibility 1-7 1.4.6 reliability 1-7 1.4.7 testability 1-8 chapter 2 functional description 2.1 pci addressing 2-1 2.1.1 con?guration space 2-1 2.1.2 pci bus commands and functions supported 2-2 2.1.3 pci cache mode 2-4 2.2 scsi functional description 2-10 2.2.1 scsi core 2-10 2.2.2 dma core 2-11 2.2.3 scripts processor 2-11 2.2.4 internal scripts ram 2-11 2.2.5 sdms: the total scsi solution 2-12 2.2.6 prefetching scripts instructions 2-13 2.2.7 opcode fetch burst capability 2-14 2.3 external memory interface 2-14 2.4 pci cache mode 2-17 viii contents 2.4.1 load and store instructions 2-17 2.4.2 3.3 v/5 v pci interface 2-17 2.4.3 additional access to general purpose pins 2-17 2.4.4 jtag boundary scan testing 2-18 2.4.5 big and little endian support 2-19 2.4.6 loopback mode 2-20 2.4.7 parity options 2-21 2.4.8 dma fifo 2-23 2.4.9 scsi bus interface 2-27 2.4.10 select/reselect during selection/reselection 2-33 2.4.11 synchronous operation 2-33 2.4.12 achieving optimal scsi send rates 2-34 2.4.13 interrupt handling 2-35 2.4.14 chained block moves 2-42 2.5 power management 2-46 2.5.1 power state d0 2-46 2.5.2 power state d3 2-46 chapter 3 signal descriptions 3.1 pci bus interface signals 3-6 3.1.1 system signals 3-6 3.1.2 address and data signals 3-7 3.1.3 interface control signals 3-8 3.1.4 arbitration signals 3-9 3.1.5 error reporting signals 3-9 3.1.6 scsi bus interface signals 3-10 3.1.7 additional interface signals 3-11 3.1.8 external memory interface signals 3-14 3.1.9 jtag signals 3-15 3.2 mad bus programming 3-15 chapter 4 registers 4.1 con?guration registers 4-1 4.2 operating registers 4-18 contents ix chapter 5 scsi scripts instruction set 5.1 low level register interface mode 5-1 5.2 high level scsi scripts mode 5-2 5.2.1 sample operation 5-3 5.3 block move instructions 5-6 5.3.1 first dword 5-6 5.3.2 second dword 5-13 5.4 i/o instruction 5-14 5.4.1 first dword 5-14 5.4.2 second dword 5-23 5.5 read/write instructions 5-24 5.5.1 first dword 5-24 5.5.2 second dword 5-26 5.5.3 read-modify-write cycles 5-26 5.5.4 move to/from sfbr cycles 5-27 5.6 transfer control instructions 5-29 5.6.1 first dword 5-29 5.6.2 second dword 5-36 5.7 memory move instructions 5-36 5.7.1 first dword 5-37 5.7.2 read/write system memory from scripts 5-38 5.7.3 second dword 5-38 5.7.4 third dword 5-38 5.8 load and store instructions 5-40 5.8.1 first dword 5-41 5.8.2 second dword 5-42 chapter 6 speci?cations 6.1 dc characteristics 6-1 6.2 tolerant technology electrical characteristics 6-7 6.3 ac characteristics 6-11 6.4 pci and external memory interface timing diagrams 6-13 6.4.1 target timing 6-15 6.4.2 initiator timing 6-24 6.4.3 external memory timing 6-32 x contents 6.5 pci and external memory interface timing 6-44 6.6 scsi timing diagrams 6-45 6.7 package drawings 6-52 appendix a register summary appendix b external memory interface diagram examples index customer feedback figures 1.1 LSI53C825A external memory interface 1-9 1.2 LSI53C825A chip block diagram 1-10 2.1 dma fifo sections 2-23 2.2 LSI53C825A host interface data paths 2-27 2.3 LSI53C825A differential wiring diagram 2-31 2.4 regulated termination 2-32 2.5 determining the synchronous transfer rate 2-35 2.6 block move and chained block move instructions 2-45 3.1 LSI53C825A pin diagram 3-2 3.2 LSI53C825Aj pin diagram 3-3 3.3 LSI53C825A functional signal grouping 3-5 5.1 scripts overview 5-5 5.2 block move instruction register 5-8 5.3 i/o instruction register 5-17 5.4 read/write instruction register 5-25 5.5 transfer control instruction 5-31 5.6 memory move instruction 5-39 5.7 load and store instruction format 5-43 6.1 rise and fall time test conditions 6-9 6.2 scsi input filtering 6-9 6.3 hysteresis of scsi receivers 6-9 6.4 input current as a function of input voltage 6-10 6.5 output current as a function of output voltage 6-10 contents xi 6.6 external clock 6-11 6.7 reset input 6-12 6.8 interrupt output 6-13 6.9 pci con?guration register read 6-15 6.10 pci con?guration register write 6-16 6.11 operating register/scripts ram read 6-17 6.12 operating register/scripts ram write 6-18 6.13 external memory read 6-20 6.14 external memory write 6-22 6.15 nonburst opcode fetch 6-24 6.16 burst opcode fetch 6-25 6.17 back-to-back read 6-26 6.18 back-to-back write 6-27 6.19 burst read 6-28 6.20 burst write 6-30 6.21 read cycle, normal/fast memory ( 3 64 kbytes), single byte access 6-32 6.22 write cycle, normal/fast memory ( 3 64 kbytes), single byte access 6-33 6.23 read cycle, normal/fast memory ( 3 64 kbytes), multiple byte access 6-34 6.24 write cycle, normal/fast memory ( 3 64 kbytes), multiple byte access 6-36 6.25 read cycle, slow memory ( 3 64 kbytes) 6-38 6.26 write cycle, slow memory ( 3 64 kbytes) 6-39 6.27 read cycle, normal/fast memory ( 3 64 kbytes) 6-40 6.28 write cycle, normal/fast memory ( 3 64 kbytes) 6-41 6.29 read cycle, slow memory ( 64 kbytes) 6-42 6.30 write cycle, slow memory ( 64 kbytes) 6-43 6.31 initiator asynchronous send 6-45 6.32 initiator asynchronous receive 6-46 6.33 target asynchronous send 6-47 6.34 target asynchronous receive 6-48 6.35 initiator and target synchronous transfers 6-48 6.36 LSI53C825A 160 pin pqfp (pf) mechanical drawing 6-52 b.1 64 kbyte interface with 200 ns memory b-1 xii contents b.2 64 kbyte interface with 150 ns memory b-2 b.3 256 kbyte interface with 150 ns memory b-3 b.4 512 kbyte interface with 150 ns memory b-4 tables 2.1 pci bus commands and encoding types 2-3 2.2 external memory support 2-16 2.3 bits used for parity control and generation 2-21 2.4 scsi parity control 2-22 2.5 scsi parity errors and interrupts 2-23 2.6 differential mode 2-28 3.1 LSI53C825A, LSI53C825Aj, LSI53C825Ae, and LSI53C825Aje power and ground pins 3-4 3.2 system signals 3-6 3.3 address and data signals 3-7 3.4 interface control signals 3-8 3.5 arbitration signals 3-9 3.6 error reporting signals 3-9 3.7 scsi bus interface signals 3-10 3.8 additional interface signals 3-11 3.9 external memory interface signals 3-14 3.10 jtag signals (LSI53C825Aj, LSI53C825Aje only) 3-15 3.11 subsystem data con?guration table for the LSI53C825Ae (pci rev id 0x26) 3-16 3.12 subsystem data con?guration table for the LSI53C825A (pci rev id 0x14) revision g only 3-16 3.13 external memory support 3-17 4.1 pci con?guration register map 4-2 4.2 LSI53C825A register map 4-19 4.3 synchronous clock conversion factor 4-29 4.4 examples of synchronous transfer periods and rates for scsi-1 4-33 4.5 example transfer periods and rates for fast scsi-2 4-33 4.6 maximum synchronous offset 4-34 4.7 timeout periods 4-82 4.8 timeout periods, 50 mhz clock 4-83 5.1 scripts instructions 5-3 5.2 read/write instructions 5-27 contents xiii 6.1 absolute maximum stress ratings 6-2 6.2 operating conditions 6-2 6.3 scsi signalssd[15:0]/, sdp[1:0]/, sreq/, sack/ 6-3 6.4 scsi signalssmsg, si_o/, sc_d/, satn/, sbsy/, ssel/, srst/ 6-3 6.5 input signalsclk, sclk, gnt/, idsel, rst/, testin, diffsens, big_lit/ 6-3 6.6 capacitance 6-4 6.7 output signalsmac/_testout, req/ 6-4 6.8 output signalsirq/, sdir[15:0], sdirp0, sdirp1, bsydir, seldir, rstdir, tgs, igs, mas/[1:0], mce/, moe/, mwe/ 6-4 6.9 output signalserr/ 6-4 6.10 bidirectional signalsad[31:0], c_be[3:0], frame/, irdy/, trdy/, devsel/, stop/, perr/, par/ 6-5 6.11 bidirectional signalsgpio0_fetch/, gpio1_master/, gpio2_mas2/, gpio3, gpio4 6-5 6.12 bidirectional signalsmad[7:0] 6-6 6.13 input signalstdi, tms, tck (LSI53C825Aj only) 6-6 6.14 output signaltdo (LSI53C825Aj only) 6-6 6.15 tolerant technology electrical characteristics 6-8 6.16 external clock 6-11 6.17 reset input 6-12 6.18 interrupt output 6-13 6.19 LSI53C825A pci and external memory interface timing 6-44 6.20 initiator asynchronous send 6-45 6.21 initiator asynchronous receive 6-46 6.22 target asynchronous send 6-47 6.23 target asynchronous receive 6-48 6.24 scsi-1 transfers (se 5.0 mbytes) 6-49 6.25 scsi-1 transfers (differential, 4.17 mbytes/s) 6-49 6.26 scsi-2 fast transfers (10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 40 mhz clock) 6-50 6.27 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes/s (16-bit transfers) 50 mhz clock 6-50 a.1 con?guration registers a-1 a.2 LSI53C825A register map a-2 xiv contents LSI53C825A/825ae pci to scsi i/o processor 1-1 chapter 1 introduction this chapter includes general information about the LSI53C825A and other members of the lsi53c8xx family of pci to scsi i/o processors and contains the following sections: section 1.1, general description section 1.2, package and feature options section 1.3, tolerant ? technology section 1.4, LSI53C825A bene?ts summary 1.1 general description this manual combines information on the LSI53C825A and LSI53C825Ae, which are pci to scsi i/o processors. the LSI53C825Ae is a minor modi?cation of the existing LSI53C825A product. it has all the functionality of the LSI53C825A with the addition of features to enable it to comply with the microsoft pc 97 hardware design guide. speci?cally, the LSI53C825Ae has a power management support enhancement. because there are only slight differences between them, the LSI53C825A and LSI53C825Ae are referred to as LSI53C825A throughout this technical manual. only the new enhancements are referred to as LSI53C825Ae. this technical manual assumes the user is familiar with the current and proposed standards for scsi and pci. for additional background information on these topics, please refer to the list of reference materials provided in the preface of this document. the LSI53C825A pci to scsi i/o processor brings high-performance i/o solutions to host adapter, workstation, and general computer designs, making it easy to add scsi to any pci system. it provides a local 1-2 introduction memory bus for local storage of the devices bios rom in ?ash memory or standard eproms. the LSI53C825A supports big and little endian byte addressing to accommodate a variety of data con?gurations. the LSI53C825A supports programming of local flash memory for updates to bios or scripts? programs. the LSI53C825A is a pin-for-pin replacement for the lsi53c825 pci to scsi i/o processor, although some software enhancements are needed to take advantage of the features in the LSI53C825A. the LSI53C825A performs fast 8-bit or 16-bit scsi transfers in single-ended (se) or differential mode, and improves performance by optimizing pci bus utilization. the LSI53C825A integrates a high-performance scsi core, a pci bus master dma core, and the lsi logic scsi scripts processor to meet the ?exibility requirements of scsi-3 and future scsi standards. it is designed to implement multithreaded i/o algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. the LSI53C825A is fully supported by the lsi logic storage device management system (sdms?), a software package that supports the advanced scsi protocol interface (aspi) and the ansi common access method (cam). sdms provides bios and driver support for hard disk, tape, removable media products, and cd-rom under the major pc operating systems. 1.2 package and feature options the LSI53C825A is packaged in a 160-pin plastic quad ?at pack. the device is also available, as the LSI53C825Aj, with additional pins that support jtag boundary scan testing. the jtag boundary scan signals replace the testin, mac/_testout, big_lit/, and sdirp1 pins. the devices that have been upgraded to include the power management features are the LSI53C825Ae and LSI53C825Aje. tolerant ? technology 1-3 1.2.1 pci pad power-up sequence this power-up sequence should be followed when separate power supplies are being applied to the vdd-io and vdd-core pins in a chip testing environment. following this recommended power-up sequence helps prevent potential damage to these devices. 1.2.1.1 description of the issue the universal pci pad input receiver in this cell library has all devices in a common n well attached to the 5 v core vdd supply. the p channel is powered from the vdd pci supply. in the event that the i/o vdd pci supply goes high prior to the core vdd supply, the parasitic diode between the p channel source and the n well of the device can become forward biased. this creates an excessive current ?ow between the two nodes, and it causes damage to the device. 1.2.1.2 solution for the issue in most system applications and production environments, the two vdd pins power-up simultaneously. the user should know of this potential hazard if using separate power supplies in a testing environment. either power-up the core and i/o vdd pci simultaneously, or if this is not possible, power-up the core vdd before powering up the i/o vdd pci supply. note that a power-down situation can have the same effect. the i/o must always power-down prior to the core. 1.3 tolerant ? technology the LSI53C825A features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation drives the scsi request, acknowledge, data, and parity signals high rather than passively pulled up by terminators. active negation is enabled by setting bit 7 in the scsi test three (stest3) register. 1-4 introduction tolerant receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption. tolerant receivers ?lter the scsi bus signals to eliminate unwanted transitions, without the long signal delay associated with rc-type input ?lters. this improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with scsi operations. tolerant input signal ?ltering is a built-in feature of the LSI53C825A and all lsi logic fast scsi devices. on the LSI53C825A, the user may select a ?ltering period of 30 or 60 ns, with bit 1 in the scsi test two (stest2) register. the bene?ts of tolerant technology include increased immunity to noise when the signal is going high, better performance due to balanced duty cycles, and improved fast scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power-up or power-down, so other devices on the bus are also protected from data corruption. tolerant technology is compatible with both the alternative one and alternative two termination schemes proposed by the american national standards institute. 1.4 LSI53C825A bene?ts summary this section provides an overview of the LSI53C825A features and bene?ts. it contains information on scsi performance , pci performance , integration , ease of use , flexibility , reliability, and testability . 1.4.1 scsi performance to improve scsi performance, the LSI53C825A: includes 4 kbyte internal ram for scripts instruction storage scsi synchronous offset increased from 8 to 16 levels supports variable block size and scatter/gather data transfers performs sustained memory-to-memory dma transfers faster than 47 mbytes/s (@ 33 mhz) minimizes scsi i/o start latency performs complex bus sequences without interrupts, including restore data pointers LSI53C825A bene?ts summary 1-5 reduces isr overhead through a unique interrupt status reporting method performs fast and wide scsi bus transfers in se and differential mode C 10 mbytes/s asynchronous 20 mbytes/s synchronous load/store scripts instruction increases performance of data transfers to and from chip registers supports target disconnect and later reconnect with no interrupt to the system processor supports multithreaded i/o algorithms in scsi scripts with fast i/o context switching expanded register move instruction supports additional arithmetic capability complies with pci bus power management speci?cation (LSI53C825Ae), revision 1.0 1.4.2 pci performance to improve pci performance, the LSI53C825A: complies with pci 2.1 speci?cation bursts 2, 4, 8, 16, 32, 64, or 128 dwords across pci bus supports 32-bit word data bursts with variable burst lengths prefetches up to 8 dwords of scripts instructions bursts scripts opcode fetches across the pci bus performs zero wait-state bus master data bursts faster than 110 mbytes/s (@ 33 mhz) supports pci cache line size register supports pci write and invalidate, read line, and read multiple commands 1-6 introduction 1.4.3 integration the LSI53C825A contains these integration features: 3.3 v/5 v pci interface full 32-bit pci dma bus master can be used as a third-party pci bus dma controller by using memory-to-memory move instructions high-performance scsi core integrated scripts processor 1.4.4 ease of use the LSI53C825A provides ease of use by having: up to one megabyte of add-in memory support for bios and scripts storage direct pci to scsi connection reduced scsi development effort easily adapted to the aspi or the ansi cam, with sdms software compiler compatible with existing lsi53c7xx and lsi53c8xx family scripts direct connection to pci, scsi se, and differential buses development tools and sample scsi scripts available maskable and pollable interrupts wide scsi, a or p cable, and up to 16 devices supported three programmable scsi timers: select/reselect, handshake-to- handshake, and general purpose. the time-out period is programmable from 100 m s to greater than 25.6 seconds sdms software for complete pc-based operating system support support for relative jumps scsi selected as id bits (ssaid) for responding with multiple ids LSI53C825A bene?ts summary 1-7 1.4.5 flexibility the LSI53C825A contains these ?exibility features: high level programming interface (scsi scripts) programs local memory bus flash memory big/little endian support selectable 88-byte or 536-byte dma fifo for backward compatibility tailored scsi sequences execute from main system ram or internal scripts ram flexible programming interface to tune i/o performance or to adapt to unique scsi devices support for changes in the logical i/o interface de?nition low level access to all registers and all scsi bus signals fetch, master, and memory access control pins separate scsi and system clocks selectable irq pins disable bit 32 additional scratch pad registers ability to route system clock to scsi clock 1.4.6 reliability the LSI53C825A contains these reliability features: 2 kv esd protection on scsi signals typical 300 mv scsi bus hysteresis protection against bus re?ections due to impedance mismatches controlled bus assertion times (reduces rfi, improves reliability, and eases fcc certi?cation) latch-up protection greater than 150 ma voltage feed-through protection (minimum leakage current through scsi pads) 25% of pins are power and ground power and ground isolation of i/o pads and internal chip logic 1-8 introduction tolerant technology provides: C active negation of scsi data, parity, request, and acknowledge signals for improved fast scsi transfer rates C input signal ?ltering on scsi receivers improves data integrity, even in noisy cabling environments jtag boundary scan support (LSI53C825Aj only) 1.4.7 testability the LSI53C825A contains these testability features: all scsi signals accessible through programmed i/o scsi loopback diagnostics scsi bus signal continuity checking support for single-step mode operation test mode (and tree) to check pin continuity to the board (most package options) jtag boundary scan support (LSI53C825Aj only) a system diagram showing the connections of the LSI53C825A with an external rom or flash memory is pictured in figure 1.1 . a block diagram of the LSI53C825A is pictured in figure 1.2 . LSI53C825A bene?ts summary 1-9 figure 1.1 LSI53C825A external memory interface pci bus scsi bus big_lit LSI53C825A gpio2_mas2/ mas1/ mwe/ moe/ mce/ mad[7:0] mas0/ gpio4 v pp translator v pp (optional) v pp hct374 hct374 hct374 rom or flash d[7:0] a[7:0] a[15:8] a[19:16] (optional) memory 1-10 introduction figure 1.2 LSI53C825A chip block diagram pci master and slave control block data fifo 536 bytes memory control scsi scripts processor operating registers con?guration registers scripts ram scsi fifo and scsi control block local bus memory tolerant drivers and receivers scsi bus external memory pci LSI53C825A/825ae pci to scsi i/o processor 2-1 chapter 2 functional description chapter 2 is divided into the following sections: section 2.1, pci addressing section 2.2, scsi functional description section 2.3, external memory interface section 2.4, pci cache mode section 2.5, power management 2.1 pci addressing there are three physical pci-de?ned address spaces: pci con?guration space i/o space memory space 2.1.1 con?guration space con?guration space is a contiguous 256 x 8-bit set of addresses dedicated to each slot or stub on the bus. decoding c_be/[3:0] determines if a pci cycle is intended to access con?guration register space. the idsel bus signal is a chip select that allows access to the con?guration register space only. a con?guration read/write cycle without idsel is ignored. the eight lower order addresses are used to select a speci?c 8-bit register. ad[10:8] are decoded as well, but they must be zero or the LSI53C825A does not respond. according to the pci speci?cation, ad[10:8] are to be used for multifunction devices. the host processor uses the pci con?guration space to initialize the LSI53C825A. 2-2 functional description the lower 128 bytes of the LSI53C825A con?guration space hold system parameters while the upper 128 bytes map into the LSI53C825A operating registers. for all pci cycles except con?guration cycles, the LSI53C825A registers are located on the 256-byte block boundary de?ned by the base address assigned through the con?gured register. the LSI53C825A operating registers are available in both the upper and lower 128-byte portions of the 256-byte space selected. at initialization time, each pci device is assigned a base address (in the case of the LSI53C825A, the upper 24 bits of the address are selected) for memory accesses and i/o accesses. on every access, the LSI53C825A compares its assigned base addresses with the value on the address/data bus during the pci address phase. if the upper 24 bits match, the access is for the LSI53C825A and the low-order eight bits de?ne the register to be accessed. a decode of c_be/ [3:0] determines which registers and what type of access is to be performed. i/o space C pci de?nes memory space as a contiguous 32-bit memory address that is shared by all system resources, including the LSI53C825A. base address one (memory) determines which 256-byte memory area this device will occupy. memory space C pci de?nes i/o space as a contiguous 32-bit i/o address that is shared by all system resources, including the LSI53C825A. base address zero (i/o) determines which 256-byte i/o area this device will occupy. 2.1.2 pci bus commands and functions supported bus commands indicate to the target the type of transaction the master is requesting. bus commands are encoded on the c_be/[3:0] lines during the address phase. pci bus command encoding and types appear in table 2.1 . pci addressing 2-3 2.1.2.1 i/o read command the i/o read command reads data from an agent mapped in i/o address space. all 32 address bits are decoded. 2.1.2.2 i/o write command the i/o write command writes data to an agent when mapped in i/o address space. all 32 address bits are decoded. table 2.1 pci bus commands and encoding types c_be[3:0] command type supported as master supported as slave 0000 special interrupt acknowledge no no 0001 special cycle no no 0010 i/o read cycle yes yes 0011 i/o write cycle yes yes 0100 reserved n/a n/a 0101 reserved n/a n/a 0110 memory read yes yes 0111 memory write yes yes 1000 reserved n/a n/a 1001 reserved n/a n/a 1010 con?guration read no yes 1011 con?guration write no yes 1100 memory read multiple yes 1 no (defaults to 0110) 1101 dual address cycle no no 1110 memory read line yes 2 no (defaults to 0110) 1111 memory write and invalidate yes 3 no (defaults to 0111) 1. this operation is selectable by bit 2 in the dma mode (dmode) operating register. 2. this operation is selectable by bit 3 in the dma mode (dmode) operating register. 3. this operation is selectable by bit 0 in the chip test three (ctest3) operating register. 2-4 functional description 2.1.2.3 memory read command the memory read command reads data from an agent mapped in memory address space. all 32 address bits are decoded. 2.1.2.4 memory write command the memory write command writes data to an agent when mapped in memory address space. all 32 address bits are decoded. 2.1.2.5 memory read multiple command the memory read multiple command reads data from an agent mapped in memory address space. all 32 address bits are decoded. 2.1.2.6 memory read line command the memory read line command reads data from an agent mapped in memory address space. all 32 address bits are decoded. 2.1.2.7 memory write and invalidate command the memory write and invalidate command writes data to an agent when mapped in memory address space. all 32 address bits are decoded. 2.1.3 pci cache mode the LSI53C825A supports the pci speci?cation for an 8-bit cache line size register located in pci con?guration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands read line, read multiple, and write and invalidate are each software enabled or disabled to allow the user full ?exibility in using these commands. 2.1.3.1 support for pci cache line size register the LSI53C825A supports the pci speci?cation for an 8-bit cache line size register in pci con?guration space. it can sense and react to nonaligned addresses corresponding to cache line boundaries. pci addressing 2-5 2.1.3.2 selection of cache line size the cache logic selects a cache line size based on the values for the burst size in the dma mode (dmode) register, bit 2 in the chip test five (ctest5) register, and the pci cache line size register. note: the LSI53C825A does not automatically use the value in the pci cache line size register as the cache line size value. the chip scales the value of the cache line size register down to the nearest binary burst size allowed by the chip (2, 4, 8, 16, 32, 64, or 128), compares this value to the burst size de?ned by the values of the dma mode (dmode) register and bit 2 of the chip test five (ctest5) register, then selects the smallest as the value for the cache line size. the LSI53C825A uses this value for all burst data transfers. 2.1.3.3 alignment the LSI53C825A uses the calculated line size value to monitor the current address for alignment to the cache line size. when it is not aligned, the chip attempts to align to the cache boundary by using a smart aligning scheme. this means that it attempts to use the largest burst size possible that is less than the cache line size, to reach the cache boundary quickly with no over?ow. this process is a stepping mechanism that steps up to the highest possible burst size based on the current address. the stepping process begins at a 4 dword boundary. the LSI53C825A will ?rst try to align to a 4 dword boundary (0x00, 0x010, 0x020, etc.) by using single dword transfers (no bursting). once this boundary is reached the chip evaluates the current alignment to various burst sizes allowed, and selects the largest possible as the next burst size, while not exceeding the cache line size. the chip then issues this burst, and reevaluates the alignment to various burst sizes, again selecting the largest possible while not exceeding the cache line size, as the next burst size. this stepping process continues until the chip reaches the cache line size boundary or runs out of data. once a cache line boundary is reached, the chip uses the cache line size as the burst size from then on, except in the case of multiples (explained below). the alignment process is ?nished at this point. 2-6 functional description example: cache line size - 16, current address = 0x01 C the chip is not aligned to a 4 dword cache boundary (the stepping threshold), so it issues four single dword transfers (the ?rst is a 3-byte transfer). at address 0x10, the chip is aligned to a 4 dword boundary, but not aligned to any higher burst size boundaries that are less than the cache line size. so, the part issues a burst of 4. at this point, the address is 0x20, and the chip evaluates that it is aligned not only t oa4dword boundary, but also to an 8 dword boundary. it selects the highest, 8, and burst 8 dwords. at this point, the address is 0x40, which is a cache line size boundary. alignment stops, and the burst size from then on is switched to 16. 2.1.3.4 memory move misalignment the LSI53C825A does not operate in a cache alignment mode when a memory move instruction type is issued and the read and write addresses are different distances from the nearest cache line boundary. for example, if the read address is 0x21f and the write address is 0x42f, and the cache line size is 8, the addresses are byte aligned, but they are not the same distance from the nearest cache boundary. the read address is 1 byte from the cache boundary 0x220 and the write address is 17 bytes from the cache boundary 0x440. in this situation, the chip does not align to cache boundaries and operates as a lsi53c825. 2.1.3.5 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register at address 0x0c in pci con?guration space. the LSI53C825A enables memory write and invalidate cycles when bit 0 in the chip test three (ctest3) register (wrie) and bit 4 in the pci command register are set. when the following conditions are met, memory write and invalidate commands are issued: the clse bit, wrie bit, and pci con?guration command register, bit 4 are set. pci addressing 2-7 the cache line size register contains a legal burst size in dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dma mode (dmode) burst size. the chip has enough bytes in the dma fifo (dfifo) to complete at least one full cache line burst. the chip is aligned to a cache line boundary. when these conditions are met, the LSI53C825A issues a write and invalidate command instead of a memory write command during all pci write cycles. multiple cache line transfers C the write and invalidate command can write multiple cache lines of data in a single bus ownership. the chip issues a burst transfer as soon as it reaches a cache line boundary. the size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size speci?ed in the revision 2.1 of the pci speci?cation. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size being that determined from the dma mode (dmode) burst size bits and chip test five (ctest5) , bit 2. if multiple cache line size transfers are not desired, the dma mode (dmode) burst size to exactly the cache line size and the chip only issues single cache line transfers. after each data transfer, the chip reevaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, no larger than the dmode burst size. the most likely scenario of this scheme is that the chip selects the dmode burst size after alignment, and issue bursts of this size. the burst size is, in effect, throttled down toward the end of a long memory move or block move transfer until only the cache line size burst size is left. the chip ?nishes the transfer with this burst size. latency C in accordance with the pci speci?cation, the latency timer is ignored when issuing a write and invalidate command such that when a latency time-out occurs, the LSI53C825A continues to transfer up until a cache line boundary. at that point, the chip relinquishes the bus, and ?nishes the transfer at a later time using another bus ownership. if the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. 2-8 functional description pci target retry C during a write and invalidate transfer, if the target device issues a retry (stop with no trdy, indicating that no data was transferred), the chip relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip issues another write and invalidate command on the next ownership, in accordance with the pci speci?cation. pci target disconnect C during a write and invalidate transfer, if the target device issues a disconnect the LSI53C825A relinquishes the bus and immediately tries to ?nish the transfer on another bus ownership. the chip does not issue another write and invalidate command on the next ownership unless the address is aligned. 2.1.3.6 memory read line command this command is identical to the memory read command, except that it additionally indicates that the master intends to fetch a complete cache line. this command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading up to a cache line boundary rather than a single memory cycle. the read line mode function that exists in the previous lsi53c8xx chips has been modi?ed in the LSI53C825A to re?ect the pci cache line size register speci?cations. the functionality of the enable read line bit (bit 3 in dma mode (dmode) ) has been modi?ed to more resemble the write and invalidate mode in terms of conditions that must be met before a read line command is issued. however, the read line option operates exactly like the previous lsi53c8xx chips when cache mode is disabled by a clse bit reset or when certain conditions exist in the chip (explained below). the read line mode is enabled by setting bit 3 in the dma mode (dmode) register. if cache mode is disabled, read line commands are issued on every read data transfer, except opcode fetches, as in previous lsi53c8xx chips. if cache mode is enabled, a read line command is issued on all read cycles, except opcode fetches, when the following conditions are met: the clse and enable read line bits are set. the cache line size register contains a legal burst size value in dwords (2, 4, 8, 16, 32, 64, or 128) that value is less than or equal to the dmode burst size. pci addressing 2-9 the number of bytes to be transferred at the time a cache boundary is reached is equal to or greater than the dmode burst size. the chip is aligned to a cache line boundary. when these conditions are met, the chip issues a read line command instead of a memory read during all pci read cycles. otherwise, it issues a normal memory read command. 2.1.3.7 memory read multiple command this command is identical to the memory read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. the LSI53C825A supports pci read multiple functionality and issues read multiple commands on the pci bus when the read multiple mode is enabled. this mode is enabled by setting bit 2 of the dma mode (dmode) register (ermp). if cache mode is enabled, a read multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met: the clse and ermp bits are set. the cache line size register contains a legal burst size value in dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dmode burst size. the number of bytes to be transferred at the time a cache line boundary has been reached must be at least twice the full cache line size. the chip is aligned to a cache line boundary. when these conditions are met, the chip issues a read multiple command instead of a memory read during all pci read cycles. burst size selection C the read multiple command reads in multiple cache lines of data in a single bus ownership. the number of cache lines to be read is a multiple of the cache line size as allowed for in the revision 2.1 of the pci speci?cation. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size determined from the dmode burst size bits and chip test five (ctest5) , bit 2. 2-10 functional description 2.1.3.8 read multiple with read line enabled when both the read multiple and read line modes are enabled, the read line command is not issued if the above conditions are met. instead, a read multiple command is issued, even though the conditions for read line are met. if the read multiple mode is enabled and the read line mode is disabled, read multiple commands are issued if the read multiple conditions are met. 2.1.3.9 unsupported pci commands the LSI53C825A does not respond to reserved commands, special cycle, dual address cycle, or interrupt acknowledge commands as a slave. it never generates these commands as a master. 2.2 scsi functional description the LSI53C825A is composed of three functional blocks: the scsi core , the dma core , and the scripts processor . the LSI53C825A is fully supported by the sdms, a complete software package that supports the lsi logic product line of scsi processors and controllers. the pci bus power management support (LSI53C825Ae) is discussed at the end of this chapter. 2.2.1 scsi core the scsi core supports the 8-bit or 16-bit data bus. it supports scsi synchronous transfer rates up to 20 mbytes/s, and asynchronous transfer rates up to 10 mbytes/s on a 16-bit wide scsi bus. the scsi core can be programmed with scsi scripts, making it easy to ?ne tune the system for speci?c mass storage devices or scsi-3 requirements. the scsi core offers low level register access or a high level control interface. like ?rst generation scsi devices, the LSI53C825A scsi core can be accessed as a register oriented device. the ability to sample and/or assert any signal on the scsi bus can be used in error recovery and diagnostic procedures. in support of loopback diagnostics, the scsi core may perform a self-selection and operate as both an initiator and a target. scsi functional description 2-11 the LSI53C825A scsi core is controlled by the integrated scripts processor through a high level logical interface. commands controlling the scsi core are fetched out of the main host memory or local memory. these commands instruct the scsi core to select, reselect, disconnect, wait for a disconnect, transfer information, change bus phases and, in general, implement all aspects of the scsi protocol. the scripts processor is a special high speed processor optimized for scsi protocol. 2.2.2 dma core the dma core is a bus master dma device that attaches directly to the industry standard pci bus. the dma core is tightly coupled to the scsi core through the scripts processor, which supports uninterrupted scatter/gather memory operations. the LSI53C825A supports 32-bit memory and automatically supports misaligned dma transfers. a 536-byte fifo allows the LSI53C825A to support 2, 4, 8, 16, 32, 64, or 128 longword bursts across the pci bus interface. 2.2.3 scripts processor the scsi scripts processor allows both dma and scsi commands to be fetched from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores and are executed from 32-bit system ram. the scripts processor executes complex scsi bus sequences independently of the host cpu. the scripts processor can begin a scsi i/o operation in approximately 500 ns. this compares with 2C8 ms required for traditional intelligent host adapters. algorithms may be designed to tune scsi bus performance, to adjust to new bus device types (such as scanners, communication gateways, etc.), or to incorporate changes in the scsi-2 or scsi-3 logical bus de?nitions without sacri?cing i/o performance. scsi scripts are hardware independent, so they can be used interchangeably on any host or cpu system bus. 2.2.4 internal scripts ram the LSI53C825A has 4 kbytes (1024 x 32 bits) of internal, general purpose ram. the ram is designed for scripts program storage, but is not limited to this type of information. when the chip fetches scripts 2-12 functional description instructions or table indirect information from the internal ram, these fetches remain internal to the chip and do not use the pci bus. other types of access to the ram by the LSI53C825A use the pci bus, as if they were external accesses. the mad5 pin enables the 4 k internal ram. to disable the internal ram, connect a 4.7 k w resistor between the mad5 pin and v ss . the ram can be relocated by the pci system bios anywhere in 32-bit address space. the ram base address register in pci con?guration space contains the base address of the internal ram. this register is similar to the rom base address register in pci con?guration space. to simplify loading of scripts instructions, the base address of the ram will appear in the scratch register b (scratchb) register when bit 3 of the chip test two (ctest2) register is set. the ram is byte accessible from the pci bus and is visible to any bus mastering device on the bus. external accesses to the ram (i.e., by the cpu) follow the same timing sequence as a standard slave register access, except that the target wait states required drop from 5 to 3. a complete set of development tools is available for writing custom drivers with scsi scripts. for more information on the scsi scripts instructions supported by the LSI53C825A, see chapter 5, scsi scripts instruction set. 2.2.5 sdms: the total scsi solution for users who do not need to develop custom drivers, lsi logic provides a total scsi solution in pc environments with the sdms. sdms software provides bios driver support for hard disk, tape, and removable media peripherals for the major pc-based operating systems. sdms software includes a scsi bios to manage all scsi functions related to the device. it also provides a series of scsi device drivers that support most major operating systems. sdms software supports a multithreaded i/o application programming interface (api) for user developed scsi applications. sdms software supports both the aspi and cam scsi software speci?cations. scsi functional description 2-13 2.2.6 prefetching scripts instructions when enabled (by setting the prefetch enable bit in the dma control (dcntl) register), the prefetch logic in the LSI53C825A fetches 8 dwords of instructions. the prefetch logic automatically determines the maximum burst size that it can perform, based on the burst length as determined by the values in the dma mode (dmode) register. if the unit cannot perform bursts of at least 4 dwords, it disables itself. while the LSI53C825A is prefetching scripts instructions, the pci cache line size register value does not have any effect and the read line, read multiple, and write and invalidate commands are not used. the LSI53C825A may ?ush the contents of the prefetch unit under certain conditions, listed below, to ensure that the chip always operates from the most current version of the software. when one of these conditions apply, the contents of the prefetch unit are ?ushed automatically. on every memory move instruction. the memory move instruction is often used to place modi?ed code directly into memory. to make sure that the chip executes all recent modi?cations, the prefetch unit ?ushes its contents and loads the modi?ed code every time an instruction is issued. to avoid inadvertently ?ushing the prefetch unit contents, use the no flush option for all memory move operations that do not modify code within the next 8 dwords. for more information on this instruction, refer to section 5.7, memory move instructions, in chapter 5, scsi scripts instruction set. on every store instruction. the store instruction may also be used to place modi?ed code directly into memory. to avoid inadvertently ?ushing the prefetch unit contents, use the no flush option for all store operations that do not modify code within the next 8 dwords. on every write to the dsp. on all transfer control instructions when the transfer conditions are met. this is necessary because the next instruction to be executed is not the sequential next instruction in the prefetch unit. when the prefetch flush bit ( dma control (dcntl) , bit 6) is set. the unit ?ushes whenever this bit is set. the bit is self-clearing. 2-14 functional description 2.2.7 opcode fetch burst capability setting the burst opcode fetch enable bit in the dma mode (dmode) register (0x38) causes the LSI53C825A to burst in the ?rst two longwords of all instruction fetches. if the instruction is a memory-to-memory move, the third longword is accessed in a separate ownership. if the instruction is an indirect type, the additional longword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move, the chip uses two accesses to obtain the four longwords required, in two bursts of two longwords each. note: this feature is only useful if prefetching is disabled. 2.3 external memory interface the LSI53C825A supports up to one megabyte of external memory in binary increments from 16 kbytes, to allow the use of expansion rom for add-in pci cards. the device also supports flash rom updates through the add-in interface and the gpio4 pin (used to control v pp , the power supply for programming external memory). this interface is designed for low speed operations such as downloading instruction code from rom; it is not intended for dynamic activities such as executing instructions. system requirements include the LSI53C825A, two or three external 8-bit address holding registers (hct273 or hct374), and the appropriate memory device. the 4.7 k w pull-down resistors on the mad bus require hc or hct external components to be used. if in-system flash rom updates are required, a 7406 (high voltage open collector inverter), an mtd4p05, and several passive components are also needed. the memory size and speed is determined by pull-down resistors on the 8-bit bidirectional memory bus at power-up. the LSI53C825A senses this bus shortly after the release of the reset signal and con?gures the rom base address register and the memory cycle state machines for the appropriate conditions. the external memory interface works with a variety of rom sizes and speeds. an example set of interface drawings is in appendix b, external memory interface diagram examples. external memory interface 2-15 the LSI53C825A supports a variety of sizes and speeds of expansion rom, using pull-down resistors on the mad[3:0] pins. the encoding of pins mad[3:1] allows the user to de?ne how much external memory is available to the LSI53C825A. table 2.2 shows the memory space associated with the possible values of mad[3:1]. the mad[3:1] pins are fully de?ned in chapter 4, registers. 2-16 functional description to use one of the con?gurations mentioned above in a host adapter board design, put 4.7 k w pull-down resistors on the mad pins corresponding to the available memory space. for example, to connect to a 32 kbyte external rom, use pull-downs on mad3 and mad2. if the external memory interface is not used, then no external resistors are necessary since there are internal pull-ups on the mad bus. the internal pull-up resistors are disabled when external pull-down resistors are detected, to reduce current drain. the LSI53C825A allows the system to determine the size of the available external memory using the expansion rom base address register in pci con?guration space. for more information on how this works, refer to the pci speci?cation or the expansion rom base address register description in chapter 3, signal descriptions. mad0 is the slow rom pin. when pulled down, it enables two extra clock cycles of data access time to allow use of slower memory devices. the external memory interface also supports updates to ?ash memory. the 12 v power supply for ?ash memory, v pp , is enabled and disabled with the gpio4 pin and the gpio4 control bit. for more information on the gpio4 pin, refer to chapter 4, registers. table 2.2 external memory support mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present pci cache mode 2-17 2.4 pci cache mode the LSI53C825A supports the pci speci?cation for an 8-bit cache line size register located in pci con?guration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cache line size register, the pci commands read line, read multiple, and write and invalidate are each software enabled or disabled to allow the user full ?exibility in using these commands. for more information on pci cache mode operations, refer to chapter 3, signal descriptions. 2.4.1 load and store instructions the LSI53C825A supports the load and store instruction type, which simpli?es the movement of data between memory and the internal chip registers. it also enables the LSI53C825A to transfer bytes to addresses relative to the data structure address (dsa) register. for more information on the load and store instructions, refer to chapter 5, scsi scripts instruction set. 2.4.2 3.3 v/5 v pci interface the LSI53C825A can attach directly to a 3.3 v or a 5 v pci interface, due to separate v dd pins for the pci bus drivers. this allows the devices to be used on the universal board recommended by the pci special interest group. 2.4.3 additional access to general purpose pins the LSI53C825A can access the gpio0 and gpio1 general purpose pins through register bits in the pci con?guration space, instead of using the general purpose pin control (gpcntl) register in the operating register space to control these pins. in the lsi logic sdms software, the con?guration bits control pins as the clock and data lines, respectively. to access the gpio[1:0] pins through the con?guration space, connect a 4.7 k w resistor between the mad7 pin and v ss . mad7 contains an internal pull-up that is sensed shortly after chip reset. if the pin is sensed high, gpio[1:0] access is disabled; if it is low, gpio[1:0] access is enabled. additionally, if gpio[1:0] access has been enabled through the 2-18 functional description mad7 pin and if gpio0 and/or gpio1 are sensed low after chip reset, gpio[1:0] access is disabled. if gpio[1:0] access through con?guration space is enabled, the gpio0 and gpio1 pins cannot be controlled from the general purpose pin control (gpcntl) and general purpose (gpreg) registers, but are observable from the general purpose (gpreg) register. when gpio[1:0] access is enabled, the serial interface control register at con?guration addresses 0x34C0x35 controls the gpio0 and gpio1 pins. for more information on gpio[1:0] access, refer to the serial interface control register description in chapter 3, signal descriptions. for more information on the gpio pins, see chapter 4, registers. this does not apply to the LSI53C825Ae. note: the lsi logic sdms software controls the gpio0 and gpio1 pins using the general purpose pin control (gpcntl) and general purpose (gpreg) registers. therefore, if using sdms, do not connect a 4.7 k w resistor between mad7 and v ss . 2.4.4 jtag boundary scan testing the LSI53C825Aj includes support for jtag boundary scan testing in accordance with the ieee 1149.1 speci?cation, with one exception that is discussed in this section. the device can accept all required boundary scan instructions, as well as the optional clamp, high-z, and idcode instructions. the LSI53C825Aj uses an 8-bit instruction register to support all boundary scan instructions. the data registers included in the device are the boundary data register, the idcode register, and the bypass register. the device can handle a 10 mhz tck frequency for tdo and tdi. due to design constrains, the rst/ pin (system reset) always 3-states the scsi pins when it is asserted. this action cannot be controlled by the boundary scan logic, and thus is not compliant with the speci?cation. there are two solutions that resolve this issue: use the rst/ pin as a boundary scan compliance pin. when the pin is deasserted, the device is boundary scan compliant and when asserted, the device is noncompliant. to maintain compliance, the rst/ pin must be driven high. pci cache mode 2-19 when rst/ is asserted during boundary scan testing, the expected output on the scsi pins must be high-z condition, and not what is contained in the boundary scan data registers for the scsi pin output cells. because of package limitations, the LSI53C825Aj replaces the testin, mac/_testout, big_lit, and sdirp1 signals with the jtag boundary scan signals. 2.4.5 big and little endian support the LSI53C825A supports both big and little endian byte ordering through pin selection. the LSI53C825Aj operates in little endian mode only (the big_lit pin is replaced by one of the jtag boundary scan signals). in big endian mode, the ?rst byte of an aligned scsi to pci transfer is routed to lane three and succeeding transfers are routed to descending lanes. this mode of operation also applies to data transfers over the add-in rom interface. the byte of data accessed at location 0x0000 from memory is routed to lane three, and the data at location 0x0003 is routed to byte lane 0. in little endian mode, the ?rst byte of an aligned scsi to pci transfer is routed to lane zero and succeeding transfers are routed to ascending lanes. this mode of operation also applies to the add-in rom interface. the byte of data accessed at location 0x0000 from memory is routed to lane zero, and the data at location 0x0003 is routed to byte lane 3. the big_lit pin gives the LSI53C825A the ?exibility of operating with either big or little endian byte orientation. internally, in either mode, the actual byte lanes of the dma fifo and registers are not modi?ed. the LSI53C825A supports slave accesses in big or little endian mode. when a dword is accessed, no repositioning of the individual bytes is necessary since dwords are addressed by the address of the least signi?cant byte. scripts always uses dwords in 32-bit systems, so compatibility is maintained between systems using different byte orientations. when less than a dword is accessed, individual bytes must be repositioned. internally, the LSI53C825A adjusts the byte control logic of the dma fifo and register decodes to access the appropriate byte lanes. the registers always appear on the same byte lane, but the address of the register are repositioned. 2-20 functional description big/little endian mode selection has the most effect on individual byte access. internally, the LSI53C825A adjusts the byte control logic of the dma fifo and register decodes to enable the appropriate byte lane. the registers always appear on the same byte lane, but the address of the register are repositioned. data to be transferred between system memory and the scsi bus always starts at address zero and continues through address n C there is no byte ordering in the chip. the ?rst byte in from the scsi bus goes to address 0, the second to address 1, etc. going out onto the scsi bus, address zero is the ?rst byte out on the scsi bus, address 1 is the second byte, etc. the only difference is that in a little endian system, address 0 is on byte lane 0, and in big endian mode address zero is on byte lane 3. correct scripts are generated if the scripts compiler is run on a system that has the same byte ordering as the target system. any scripts patching in memory must patch the instruction with the byte ordering that the scripts processor expects. software drivers for the LSI53C825A should access registers by their logical name (i.e., scntl0) rather than by their address. the logical name should be equated to the registers big endian address in big endian mode (scntl0 = 0x03), and its little endian address in little endian mode (scntl0 = 0x00). this way, there is no change to the software when moving from one mode to the other; only the equate statement setting the operating modes needs to be changed. addressing of registers from within a scripts instruction is independent of bus mode. internally, the LSI53C825A always operates in little endian mode. 2.4.6 loopback mode the LSI53C825A loopback mode allows testing of both initiator and target functions and, in effect, lets the chip communicate with itself. when the loopback enable bit is set in the chip test one (ctest1) register, the LSI53C825A allows control of all scsi signals, whether the LSI53C825A is operating in initiator or target mode. for more information on this mode of operation, refer to the scsi scripts processors programming guide . pci cache mode 2-21 2.4.7 parity options the LSI53C825A implements a ?exible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the scsi bus to test parity error recovery procedures. table 2.3 de?nes the bits that are involved in parity control and observation. table 2.4 describes the parity control function of the enable parity checking and assert scsi even parity bits in the scsi control zero (scntl0) register. table 2.5 describes the options available when a parity error occurs. table 2.3 bits used for parity control and generation bit name location description assert satn/ on parity errors scsi control zero (scntl0) , bit 1 causes the LSI53C825A to automatically assert satn/ when it detects a parity error while operating as an initiator. enable parity checking scsi control zero (scntl0) , bit 3 enables the LSI53C825A to check for parity errors. the LSI53C825A checks for odd parity. assert even scsi parity scsi control one (scntl1) , bit 2 determines the scsi parity sense generated by the LSI53C825A to the scsi bus. disable halt on satn/ or a parity error (target mode only) scsi control one (scntl1) , bit 5 causes the LSI53C825A not to halt operations when a parity error is detected in target mode. enable parity error interrupt scsi interrupt enable zero (sien0) , bit 0 determines whether the LSI53C825A will generate an interrupt when it detects a scsi parity error. parity error scsi interrupt status zero (sist0) , bit 0 this status bit is set whenever the LSI53C825A has detected a parity error on the scsi bus. 2-22 functional description status of scsi parity signal scsi status zero (sstat0) , bit 0 this status bit represents the active high current state of the scsi sdp0 parity signal. scsi sdp1 signal scsi status two (sstat2) , bit 0 this bit represents the active high current state of the scsi sdp1 parity signal. latched scsi parity scsi status two (sstat2) , bit 3 and scsi status one (sstat1) , bit 3 these bits re?ect the scsi odd parity signal corresponding to the data latched into the scsi input data latch (sidl) register. master parity error enable chip test four (ctest4) , bit 3 enables parity checking during master data phases. master data parity error dma status (dstat) , bit 6 set when the LSI53C825A as a master detects that a target device has signaled a parity error during a data phase. master data parity error interrupt enable dma interrupt enable (dien) , bit 6 by clearing this bit, a master data parity error will not cause irq/ to be asserted, but the status bit will be set in the dma status (dstat) register. table 2.4 scsi parity control epc aesp description 0 0 does not check for parity errors. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 0 1 does not check for parity errors. parity is generated when sending scsi data. asserts even parity when sending scsi data. 1 0 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 1 1 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts even parity when sending scsi data. 1. key: epc = enable parity checking (bit 3, scsi control zero (scntl0) ). asep = assert scsi even parity (bit 2, scsi control one (scntl1) ). 2. this table only applies when the enable parity checking bit is set. table 2.3 bits used for parity control and generation (cont.) bit name location description pci cache mode 2-23 2.4.8 dma fifo the dma fifo is 4 bytes wide by 134 transfers deep. the dma fifo is illustrated in figure 2.1 . to assure compatibility with older products in the lsi53c8xx family, the user may set the dma fifo size to 88 bytes by clearing the dma fifo size bit, bit 5 in the chip test five (ctest5) register. figure 2.1 dma fifo sections table 2.5 scsi parity errors and interrupts dph par description 0 0 halts when a parity error occurs in target or initiator mode and will not generate an interrupt. 0 1 halts when a parity error occurs in target mode and will generate an interrupt in target or initiator mode. 1 0 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt will not be generated. 1 1 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt will be generated. key: dhp = disable halt on satn/ or parity error (bit 5, scsi control one (scntl1) . par = parity error (bit 0, scsi interrupt enable zero (sien0) . 134 transfers deep . . . . . . 32 bytes wide 8 bits byte lane 3 8 bits byte lane 2 8 bits byte lane 1 8 bits byte lane 0 2-24 functional description 2.4.8.1 data paths the data path through the LSI53C825A is dependent on whether data is being moved into or out of the chip, and whether scsi data is being transferred asynchronously or synchronously. the following steps determine if any bytes remain in the data path when the chip halts an operation: asynchronous scsi send C step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between zero and 88. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between zero and 536. step 2. read bit 5 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the scsi output data latch (sodl) register. if bit 5 is set in the sstat0 or sstat2, then the least signi?cant byte or the most signi?cant byte in the scsi output data latch (sodl) register is full, respectively. checking this bit also reveals bytes left in the scsi output data latch (sodl) register from a chained move operation with an odd byte count. synchronous scsi send C step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?cant bits of the dma byte pci cache mode 2-25 counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between zero and 88. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between zero and 536. step 2. read bit 5 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the scsi output data latch (sodl) register. if bit 5 is set in the sstat0 or sstat2, then the least signi?cant byte or the most signi?cant byte in the scsi output data latch (sodl) register is full, respectively. checking this bit also reveals bytes left in the scsi output data latch (sodl) register from a chained move operation with an odd byte count. step 3. read bit 6 in the scsi status zero (sstat0) and scsi status two (sstat2) registers to determine if any bytes are left in the sodr register. if bit 6 is set in the scsi status zero (sstat0) or scsi status two (sstat2) , then the least signi?cant byte or the most signi?cant byte in the sodr register is full, respectively. asynchronous scsi receive C step 1. if the dma fifo size is set to 88 bytes, look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between zero and 88. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of 2-26 functional description bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between zero and 536. step 2. read bit 7 in the scsi status zero (sstat0) and scsi status two (sstat2) register to determine if any bytes are left in the scsi input data latch (sidl) register. if bit 7 is set in the scsi status zero (sstat0) or scsi status two (sstat2) , then the least signi?cant byte or the most signi?cant byte is full, respectively. step 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit ( scsi control two (scntl2) , bit 0) to determine whether a byte is left in the scsi wide residue (swide) register. synchronous scsi receive C step 1. if the dma fifo size is set to 88 bytes, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between zero and 88. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo (dfifo) register. and the result with 0x3ff for a byte count between zero and 536. step 2. read bits [7:4] of the scsi status one (sstat1) register and bit 4 of the scsi status two (sstat2) register, the binary representation of the number of valid bytes in the scsi fifo, to determine if any bytes are left in the scsi fifo. step 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit ( scsi control two (scntl2) , bit 0) to determine whether a byte is left in the scsi wide residue (swide) register. figure 2.2 shows how data is moved to/from the scsi bus in each of the different modes. pci cache mode 2-27 figure 2.2 LSI53C825A host interface data paths 2.4.9 scsi bus interface the LSI53C825A supports both se and differential operation. all scsi signals are active low. the LSI53C825A contains the se output drivers and can be connected directly to the scsi bus. each output is isolated from the power supply to ensure that a powered-down LSI53C825A has no effect on an active scsi bus (cmos voltage feed-through phenomena). tolerant technology provides signal ?ltering at the inputs of sreq/ and sack/ to increase immunity to signal re?ections. pci interface pci interface pci interface pci interface dma fifo (32 bits x 16) dma fifo (32 bits x 16) dma fifo (32 bits x 16) dma fifo (32 bits x 16) sodl register sidl register sodl register scsi fifo (8 or 16 bits x 16) scsi interface scsi interface sodr register scsi interface scsi interface asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive swide register swide register 2-28 functional description 2.4.9.1 differential mode in differential mode, the sdir[15:0], sdirp[1:0], igs, tgs, rstdir, bsydir, and seldir signals control the direction of external differential pair transceivers. the LSI53C825A is placed in differential mode by setting the dif bit, bit 5 of the scsi test two (stest2) register (0x4e). setting this bit 3-states the bsy/, sel/, and rst/ pads so they can be used as pure input pins. in addition to the standard scsi lines, the following signals de?ned in table 2.6 are used during differential operation by the LSI53C825A. see figure 2.3 for an example differential wiring diagram, in which the LSI53C825A is connected to the ti 75lbc976 differential transceiver. the recommended value of the pull-up resistor on the req/, ack/, msg/, c/d/, i/o/, atn/, sd[7:0]/, and sdp0/ lines is 680 w when the active negation portion of lsi logic tolerant technology is not enabled. when tolerant technology is enabled, the recommended resistor value on the req/, ack/, sd[7:0]/, and sdp0/ signals is 1.5 k w . the electrical characteristics of these pins change when tolerant is enabled, permitting a higher resistor value. table 2.6 differential mode signal function bsydir, seldir, rstdir active high signals used to enable the differential drivers as outputs for scsi signals bsy/, sel/, and rst/, respectively. sdir[15:0], sdirp[1:0] active high signals used to control direction of the differential drivers for scsi data and parity lines, respectively. igs active high signal used to control direction of the differential driver for initiator group signals atn/ and ack/. tgs active high signal used to control direction of the differential drivers for target group signals msg/, c/d/, i/o/, and req/. diffsens input to the LSI53C825A used to detect the presence of a se device on a differential system. if a logical zero is detected on this pin, then it is assumed that an se device is on the bus and all scsi outputs will be 3-stated to avoid damage to the transceiver. pci cache mode 2-29 to interface the LSI53C825A to the 75lbc976, connect the dir pins, as well as igs and tgs, of the LSI53C825A directly to the transceiver enables (nde/re/). these signals control the direction of the channels on the 75lbc976. the scsi bidirectional control and data pins (sd[7:0]/, sdp0/, req/, ack/, msg/, i_o/, c_d/, and atn/) of the LSI53C825A connect to the bidirectional data pins (na) of the 75lbc976 with a pull-up resistor. the pull-up value should be no lower than the transceiver i ol can tolerate, but not so high as to cause rc timing problems. the three remaining pins, sel/, bsy/, and rst/ are connected to the 75lbc976 with a pull-down resistor. the pull-down resistors are required when the pins (na) of the 75lbc976 are con?gured as inputs. when the data pins are inputs, the resistors provide a bias voltage to both the LSI53C825A pins (sel/, bsy/, and rst/) and the 75lbc976 data pins. because the sel/, bsy/, and rst/ pins on the LSI53C825A are inputs only, this con?guration allows for the sel/, bsy/, and rst/ scsi signals to be asserted on the scsi bus. the differential pairs on the scsi bus are reversed when connected to the 75lbc976, due to the active low nature of the scsi bus. 8-bit/16-bit scsi and the differential interface C in an 8-bit scsi bus, the sd[15:8] pins on the LSI53C825A should be pulled up with a 1.5 k w resistor or terminated like the rest of the scsi bus lines. this is very important, as errors may occur during reselection if these lines are left ?oating. in the LSI53C825Aj, the sdirp1 pin is replaced by the tck jtag signal. if the device is used in a wide differential system, use the sdirp0 pin to control the direction of the differential transceiver for both the sp0 and sp1 signals. the sdirp0 signal is capable of driving both direction inputs from a transceiver. 2.4.9.2 terminator networks the terminator networks provide the biasing needed to pull signals to an inactive voltage level, and to match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of the scsi chain, and only at the ends; no system should ever have more or less than two terminators installed and active. scsi host adapters should provide a means of 2-30 functional description accommodating terminators. the terminators should be socketed, so that if not needed they may be removed, or there should be a means of disabling them with software. se cables can use a 220 w pull-up to the terminator power supply (term power) line and a 330 w pull-down to ground. because of the high-performance nature of the LSI53C825A, regulated (or active) termination is recommended. note: if the LSI53C825A is to be used in a design with only an 8-bit scsi bus, all 16 data lines still must be terminated or pulled high. figure 2.3 is an example differential wiring diagram. figure 2.4 shows a unitrode active terminator. for additional information, refer to the scsi-2 speci?cation. tolerant active negation can be used with either termination network. pci cache mode 2-31 figure 2.3 LSI53C825A differential wiring diagram lsi53c8xx seldir bsydir rstdir sel/ bsy/ rst/ req/ ack/ msg/ c/d/ i/o/ atn/ tgs igs sd[8:15]/ sdp1/ sdirp0 sdir7 sdir6 sdir5 sdir4 sdir3 sdir2 sdir1 sdir0 sdp0/ sd7/ sd6/ sd5/ sd4/ sd3/ sd2/ sd1/ sd0/ diffsens 1.5 k 1.5 k w vdd vdd 1.5 k w 1.5 k w vdd 1.5 k w vdd vdd 1.5 k w sn75976a cde0 cde1 cde2 bsr cre 1a 1de/re 2a 2de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 3a 3de/re sel- seldir bsydir rstdir req/ bsy- rst- ack/ msg/ c_d/ i_o/ atn/ vdd 1.5 k w diffsens schottky diode diffsens (pin 21) - sel scsi bus +sel - bsy +bsy - rst (42) +rst - req +req - ack +ack - msg +msg - c/d +c/d - i/o +i/o - at n +atn 1b+ 1b - 2b+ 2b - 3b+ 3b - 4b+ 4b - 5b+ 5b - 6b+ 6b - 7b+ 7b - 8b+ 8b - 9b+ 9b - (41) (34) (33) (38) (37) (46) (45) (36) (35) (40) (39) (44) (43) (48) (47) (30) (29) sn75976a cde0 cde1 cde2 bsr cre 1a 1de/re 2a 2de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 3a 3de/re - db0 +db0 - db1 +db1 - db2 (4) +db2 - db3 +db3 - db4 +db4 - db5 +db5 - db6 +db6 - db7 +db7 - dbp +dbp 1b+ 1b - 2b+ 2b - 3b+ 3b - 4b+ 4b - 5b+ 5b - 6b+ 6b - 7b+ 7b - 8b+ 8b - 9b+ 9b - (3) (6) (5) (8) (7) (10) (9) (12) (11) (14) (13) (16) (15) (18) (17) (20) (19) diffsens diffsens sdir0 sdir1 sdir2 sdir3 sdir4 sdir5 sdir6 sdir7 sdirp0 sd0 / sd1 / sd2/ sd3/ sd4 / sd5 / sd6/ sd7/ sdp0/ 1.5 k 2-32 functional description figure 2.4 regulated termination terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 terml10 terml11 terml12 terml13 terml14 terml15 terml16 terml17 terml18 sd0 (j1.40) sd1 (j1.41) sd2 (j1.42) sd3 (j1.43) sd4 (j1.44) sd5 (j1.45) sd6 (j1.46) sd7 (j1.47) sdp (j1.48) atn (j1.55) bsy (j1.57) ack (j1.58) rst (j1.59) msg (j1.60) sel (j1.61) c/d (j1.62) req (j1.63) i/o (j1.64) 20 21 22 23 24 25 26 27 28 3 4 5 6 7 8 9 10 11 19 disconnect reg_out 2 2.85 v uc5601qp c1 c2 note: 1. c1 - 10 m f smt 2. c2 - 0.1 m f smt 3. c3 - 2.2 m f smt 4. j1 - 68-pin, high density p connector terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 sd15 (j1.38) sd14 (j1.37) sd13 (j1.36) sd12 (j1.35) sd11 (j1.68) sd10 (j1.67) sd9 (j1.66) sd8 (j1.65) sdp1 (j1.39) 10 9 8 7 3 2 1 16 15 reg_out 14 uc5603dp c3 6 disconnect pci cache mode 2-33 2.4.10 select/reselect during selection/reselection in multithreaded scsi i/o environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection. this situation may occur when a scsi controller (operating in initiator mode) tries to select a target and is reselected by another. the select scripts instruction has an alternate address to which the scripts jumps when this situation occurs. the analogous situation for target devices is being selected while trying to perform a reselection. once a change in operating mode occurs, the initiator scripts should start with a set initiator instruction or the target scripts should start with a set target instruction. the selection and reselection enable bits (scid bits 5 and 6, respectively) should both be asserted so that the LSI53C825A may respond as an initiator or as a target. if only selection is enabled, the LSI53C825A cannot be reselected as an initiator. there are also status and interrupt bits in the scsi interrupt status zero (sist0) and scsi interrupt enable zero (sien0) registers, respectively, indicating that the LSI53C825A has been selected (bit 5) and reselected (bit 4). 2.4.11 synchronous operation the LSI53C825A can transfer synchronous scsi data in both initiator and target modes. the scsi transfer (sxfer) register controls both the synchronous offset and the transfer period. it may be loaded by the cpu before scripts execution begins, from within scripts using a table indirect i/o instruction, or with a read-modify-write instruction. the LSI53C825A can receive data from the scsi bus at a synchronous transfer period as short as 80 or 160 ns (with a 50 mhz clock), regardless of the transfer period used to send data. the LSI53C825A can receive data at one-fourth of the divided sclk frequency. depending on the sclk frequency, the negotiated transfer period, and the synchronous clock divider, the LSI53C825A can send synchronous data at intervals as short as 100 ns for fast scsi and 200 ns for scsi-1. 2.4.11.1 determining the data transfer rate synchronous data transfer rates are controlled by bits in two different registers of the LSI53C825A. a brief description of the bits is provided below. 2-34 functional description 2.4.11.2 scsi control three (scntl3) register, bits [6:4] the scf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. the output from this divider controls the rate at which data can be received; this rate must not exceed 50 mhz. the receive rate of synchronous scsi data is one-fourth of the scf divider output. for example, if sclk is 40 mhz and the scf value is set to divide by one, then the maximum rate at which data can be received is 10 mhz (40/(1*4) = 10). 2.4.11.3 scsi control three (scntl3) register, bits [2:0] the ccf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the asynchronous scsi core logic. this divider must be set according to the input clock frequency in the table. 2.4.11.4 scsi transfer (sxfer) register, bits [7:5] the tp[2:0] divider bits determine the scsi synchronous transfer period when sending synchronous scsi data in either initiator or target mode. this value further divides the output from the scf divider. 2.4.12 achieving optimal scsi send rates to achieve optimal synchronous scsi send timings, the scf divisor value should be set high, to divide the clock as much as possible before presenting the clock to the tp divider bits in the scsi transfer (sxfer) register. the tp[2:0] divider value should be as low as possible. for example, with a 40 mhz clock to achieve a 5 mbytes/s send rate, the scf bits can be set to divide by 1 and the tp bits to divide by 8; or the scf bits can be set to divide by 2 and the tp bits set to divide by 2. use the second option to achieve optimal scsi timings. figure 2.5 illustrates the clock division factors used in each register, and the role of the register bits in determining the transfer rate. pci cache mode 2-35 figure 2.5 determining the synchronous transfer rate 2.4.13 interrupt handling the scripts processor in the LSI53C825A performs most functions independently of the host microprocessor. however, certain interrupt situations must be handled by the external microprocessor. this section explains all aspects of interrupts as they apply to the LSI53C825A. 2.4.13.1 polling and hardware interrupts the external microprocessor is informed of an interrupt condition by polling or hardware interrupts. polling means that the microprocessor must continually loop and read a register until it detects a bit set that indicates an interrupt. this method is the fastest, but it wastes cpu time that could be used for other system tasks. the preferred method of sclk scf divider ccf divider synchronous divider asynchronous scsi logic divide by 4 scf2 scf1 scf0 scf divisor 0011 0 1 0 1.5 0112 1003 0003 tp2 tp1 tp0 xferp divisor 0004 0015 0106 0117 1008 1019 11010 11111 ccf2 ccf1 ccf0 divisor 0011 0 1 0 1.5 0112 1003 0003 example: sclk = 40 mhz, scf = 1, xferp = 4, scsi transfer rate = 10 mhz, ccf = 2 this point must not exceed 50 mhz receive clock send clock (to scsi bus) this point must not exceed 25 mhz (40 mhz ? 1 = synchronous core rate) (40 mhz ? 4 = 10 mhz synchronous rate = 10 mbytes/s on an 8-bit scsi bus) 2-36 functional description detecting interrupts in most systems is hardware interrupts. in this case, the LSI53C825A asserts the interrupt request (irq/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine. a hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.4.13.2 registers the registers in the LSI53C825A that are used for detecting or de?ning interrupts are the interrupt status (istat) , scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , dma status (dstat) , scsi interrupt enable zero (sien0) , scsi interrupt enable one (sien1) , dma control (dcntl) , and dma interrupt enable (dien) . istat C the interrupt status (istat) is the only register that can be accessed as a slave during scripts operation, therefore it is the register that is polled when polled interrupts are used. it is also the ?rst register that should be read when the irq/ pin has been asserted in association with a hardware interrupt. the intf (interrupt-on-the-fly) bit should be the ?rst interrupt serviced. it must be written to one to be cleared. this interrupt must be cleared before servicing any other interrupts. if the sip bit in the istat register is set, then a scsi-type interrupt has occurred and the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers should be read. if the dip bit in the interrupt status (istat) register is set, then a dma-type interrupt has occurred and the dma status (dstat) register should be read. scsi-type and dma-type interrupts may occur simultaneously, so in some cases both sip and dip may be set. sist0 and sist1 C the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers contain the scsi-type interrupt bits. reading these registers determines which condition or conditions caused the scsi-type interrupt, and clears that scsi interrupt condition. if the LSI53C825A is receiving data from the scsi bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the dma fifo to memory before generating the interrupt. if the LSI53C825A is sending data to the scsi bus and a fatal scsi interrupt condition occurs, data could be left in the dma fifo. because of this the dma fifo empty (dfe) bit in dma status (dstat) should be checked. if this pci cache mode 2-37 bit is clear, set the clf (clear dma fifo) and csf (clear scsi fifo) bits before continuing. the clf bit is bit 2 in chip test three (ctest3) . the csf bit is bit 1 in chip test three (ctest3) . dstat C the dma status (dstat) register contains the dma-type interrupt bits. reading this register determines which condition or conditions caused the dma-type interrupt, and clears that dma interrupt condition. bit 7 in ds tat, dfe, is purely a status bit. it does not generate an interrupt under any circumstances and will not be cleared when read. dma interrupts ?ush neither the dma nor scsi fifos before generating the interrupt, so the dfe bit in the dma status (dstat) register should be checked after any dma interrupt. if the dfe bit is cleared, then the fifos must be cleared by setting the clf (clear dma fifo) and csf (clear scsi fifo) bits, or ?ushed by setting the flf (flush dma fifo) bit. sien0 and sien1 C the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) registers are the interrupt enable registers for the scsi interrupts in scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) . dien C the dma interrupt enable (dien) register is the interrupt enable register for dma interrupts in dma status (dstat) . dcntl C when bit 1 in this register is set, the irq/ pin is not asserted when an interrupt condition occurs. the interrupt is not lost or ignored, but merely masked at the pin. clearing this bit when an interrupt is pending immediately causes the irq/ pin to assert. as with any register other than interrupt status (istat) , this register cannot be accessed except by a scripts instruction during scripts execution. 2.4.13.3 fatal vs. nonfatal interrupts a fatal interrupt, as the name implies, always causes scripts to stop running. all nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. interrupt masking will be discussed in section 2.4.13.4, masking. all dma interrupts (indicated by the dip bit in interrupt status (istat) and one or more bits in dma status (dstat) being set) are fatal. 2-38 functional description some scsi interrupts (indicated by the sip bit in the istat and one or more bits in scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) being set) are nonfatal. when the LSI53C825A is operating in initiator mode, only the function complete (cmp), selected (sel), reselected (rsl), general purpose timer expired (gen), and handshake-to-handshake timer expired (hth) interrupts are nonfatal. when operating in target mode cmp, sel, rsl, target mode: satn/ active (m/a), gen, and hth are nonfatal. refer to the description for the disable halt on a parity error or satn/ active (target mode only) (dhp) bit in the scsi control one (scntl1) register to con?gure the chips behavior when the satn/ interrupt is enabled during target mode operation. the interrupt-on-the-fly interrupt is also nonfatal, since scripts can continue when it occurs. the reason for nonfatal interrupts is to prevent scripts from stopping when an interrupt occurs that does not require service from the cpu. this prevents an interrupt when arbitration is complete (cmp set), when the LSI53C825A has been selected or reselected (sel or rsl set), when the initiator has asserted atn (target mode: satn/ active), or when the general purpose or handshake-to-handshake timers expire. these interrupts are not needed for events that occur during high-level scripts operation. 2.4.13.4 masking masking an interrupt means disabling or ignoring that interrupt. interrupts can be masked by clearing bits in the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) (for scsi interrupts) registers or dma interrupt enable (dien) (for dma interrupts) register. how the chip responds to masked interrupts depends on: whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in initiator or target mode. if a nonfatal interrupt is masked and that condition occurs, the scripts do not stop, the appropriate bit in the sist0 or sist1 is still set, the sip bit in the istat is not set, and the irq/ pin is not asserted. see section 2.4.13.3, fatal vs. nonfatal interrupts, for a list of the nonfatal interrupts. pci cache mode 2-39 if a fatal interrupt is masked and that condition occurs, then the scripts still stop, the appropriate bit in the dma status (dstat) , scsi interrupt status zero (sist0) ,or scsi interrupt status one (sist1) register is set, and the sip or dip bit in the interrupt status (istat) is set, but the irq/ pin is not asserted. when the chip is initialized, enable all fatal interrupts if you are using hardware interrupts. if a fatal interrupt is disabled and that interrupt condition occurs, the scripts halts and the system will never know it unless it times out and checks the istat after a certain period of inactivity. if you are polling the istat instead of using hardware interrupts, then masking a fatal interrupt will make no difference since the sip and dip bits in the istat inform the system of interrupts, not the irq/ pin. masking an interrupt after irq/ is asserted does not cause irq/ to be deasserted. 2.4.13.5 stacked interrupts the LSI53C825A stacks interrupts if they occur one after the other. if the sip or dip bits in the interrupt status (istat) register are set (?rst level), then there is already at least one pending interrupt, and any future interrupts are stacked in extra registers behind the scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) registers (second level). when two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) . when the ?rst level of interrupts are cleared, all the interrupts that came in afterward will move into the scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) . after the ?rst interrupt is cleared by reading the appropriate register, the irq/ pin is deasserted for a minimum of three clks. the stacked interrupts move into the sist0, sist1, or dstat and the irq/ pin is asserted once again. since a masked nonfatal interrupt does not set the sip or dip bits, interrupt stacking does not occur. a masked, nonfatal interrupt still posts the interrupt in sist0, but does not assert the irq/ pin. since no interrupt is generated, future interrupts move right into the sist0 or 2-40 functional description sist1 instead of being stacked behind another interrupt. when another condition occurs that generates an interrupt, the bit corresponding to the earlier masked nonfatal interrupt is still set. a related situation to interrupt stacking is when two interrupts occur simultaneously. since stacking does not occur until the sip or dip bits are set, there is a small timing window in which multiple interrupts can occur but are not stacked. these could be multiple scsi interrupts (sip set), multiple dma interrupts (dip set), or multiple scsi and multiple dma interrupts (both sip and dip set). as previously mentioned, dma interrupts do not attempt to ?ush the fifos before generating the interrupt. it is important to set either the clear dma fifo (clf) and clear scsi fifo (csf) bits if a dma interrupt occurs and the dma fifo empty (dfe) bit is not set. this is because any future scsi interrupts are not posted until the dma fifo is cleared of data. these locked out scsi interrupts are posted as soon as the dma fifo is empty. 2.4.13.6 halting in an orderly fashion when an interrupt occurs, the LSI53C825A attempts to halt in an orderly fashion. if the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a bus fault. execution does not begin, but the dsp points to the next instruction since it is updated when the current instruction is fetched. if the dma direction is a write to memory and a scsi interrupt occurs, the LSI53C825A attempts to ?ush the dma fifo (dfifo) to memory before halting. under any other circumstances only the current cycle is completed before halting, so the dfe bit in dma status (dstat) should be checked to see if any data remains in the dma fifo. scsi sreq/sack handshakes that have begun are completed before halting. the LSI53C825A attempts to clean up any outstanding synchronous offset before halting. in the case of transfer control instructions, once instruction execution begins it continues to completion before halting. pci cache mode 2-41 if the instruction is a jump/call when/if 2-42 functional description 2.4.14 chained block moves since the LSI53C825A has the capability to transfer 16-bit wide scsi data, a unique situation occurs when dealing with odd bytes. the chained move (chmov) scripts instruction along with the wide scsi send (wss) and wide scsi receive (wsr) bits in the scsi control two (scntl2) register are used to facilitate these situations. 2.4.14.1 wide scsi send bit the wss bit is set whenever the scsi controller is sending data (data-out for initiator or data-in for target) and the controller detects a partial transfer at the end of a chained block move scripts instruction (this ?ag is not set if a normal block move instruction is used). under this condition, the scsi controller does not send the low-order byte of the last partial memory transfer across the scsi bus. instead, the low-order byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register and the wss ?ag is set. the hardware uses the wss ?ag to determine what behavior must occur at the start of the next data send transfer. when the wss ?ag is set at the start of the next transfer, the ?rst byte (the high-order byte) of the next data send transfer is married with the stored low-order byte in the scsi output data latch (sodl) register; and the two bytes are sent out across the bus, regardless of the type of block move instruction (normal or chained). the ?ag is automatically cleared when the married word is sent. the ?ag is alternately cleared through scripts or by the microprocessor. additionally, this bit can be used by the microprocessor or scripts for error detection and recovery purposes. 2.4.14.2 wide scsi receive bit the wsr bit is set whenever the scsi controller is receiving data (data-in for initiator or data-out for target) and the controller detects a partial transfer at the end of a block move or chained block move scripts instruction. when wsr is set, the high-order byte of the last scsi bus transfer is not transferred to memory. instead, the byte is temporarily stored in the scsi wide residue (swide) register. the hardware uses the wsr bit to determine what behavior must occur at the start of the next data receive transfer. the bit is automatically cleared at the start of the next data receive transfer. the bit can alternatively be pci cache mode 2-43 cleared by the microprocessor or through scripts. the bit can also be used by the microprocessor or scripts for error detection and recovery purposes. 2.4.14.3 swide register this register stores data for partial byte data transfers. for receive data, the scsi wide residue (swide) register holds the high-order byte of a partial scsi transfer which has not yet been transferred to memory. this stored data may be a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next block move instruction. 2.4.14.4 sodl register for send data, the low-order byte of the scsi output data latch (sodl) register holds the low-order byte of a partial memory transfer which has not yet been transferred across the scsi bus. this stored data is usually married with the ?rst byte of the next data send transfer, and both bytes are sent across the scsi bus at the start of the next data send block move command. 2.4.14.5 chained block move scripts instruction a chained block move scripts instruction is primarily used to transfer consecutive data send or data receive blocks. using the chained block move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. behavior of the chained block move instruction varies slightly for sending and receiving data. for receive data (data-in for initiator or data-out for target), a chained block move instruction indicates that if a partial transfer occurred at the end of the instruction, the wsr ?ag is set. the high-order byte of the last scsi transfer is stored in the scsi wide residue (swide) register rather than transferred to memory. the contents of the scsi wide residue (swide) register should be the ?rst byte transferred to memory at the start of the chained block move data stream. since the byte count always represents data transfers to/from memory (as opposed to the scsi bus), the byte transferred out of the scsi wide residue (swide) register is one of the bytes in the byte count. if the wsr bit is cleared when a receive data chained block move instruction is executed, the data 2-44 functional description transfer occurs similar to that of the regular block move instruction. whether the wsr bit is set or cleared, when a normal block move instruction is executed, the contents of the scsi wide residue (swide) register are ignored and the transfer takes place normally. for n consecutive wide data receive block move instructions, the 2nd through the nth block move instructions should be chained block moves. for send data (data-out for initiator or data-in for target), a chained block move instruction indicates that if a partial transfer terminates the chained block move instruction, the last low-order byte (the partial memory transfer) should be stored in the lower byte of the scsi output data latch (sodl) register and not sent across the scsi bus. without the chained block move instruction, the last low-order byte would be sent across the scsi bus. the starting byte count represents data bytes transferred from memory but not to the scsi bus when a partial transfer exists. for example, if the instruction is an initiator chained block move data out of ?ve bytes (and wss is not previously set), ?ve bytes will be transferred out of memory to the scsi controller, four bytes are transferred from the scsi controller across the scsi bus, and one byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register waiting to be married with the ?rst byte of the next block move instruction. regardless of whether a chained block move or normal block move instruction is used, if the wss bit is set at the start of a data send command, the ?rst byte of the data send command is assumed to be the high-order byte and is married with the low-order byte stored in the lower byte of the scsi output data latch (sodl) register before the two bytes are sent across the scsi bus. for n consecutive wide data send block move commands, the ?rst through the (nth C 1) block move instructions should be chained block moves. pci cache mode 2-45 the chained block move instruction is illustrated in figure 2.6 . figure 2.6 block move and chained block move instructions chmov 5, 3 when data_out moves ?ve bytes from address 0x03 in the host memory to the scsi bus. bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in the low-order byte of the scsi output data latch (sodl) register and is combined with the ?rst byte of the following move instruction. move 5, 9 when data_out moves ?ve bytes from address 0x09 in the host memory to the scsi bus. 0x03 0x02 0x01 0x00 0x07 0x06 0x05 0x04 0x0b 0x0a 0x09 0x08 0x0f 0x0e 0x0d 0x0c 0x13 0x12 0x11 0x10 0x04 0x03 0x06 0x05 0x09 0x07 0x0b 0x0a 0x0d 0x0c 32 bits 16 bits host memory scsi bus 00 04 08 0c 10 2-46 functional description 2.5 power management this feature complies with the pci bus power management interface speci?cation, revision 1.0. the pci function power states are de?ned in that speci?cation: d0, d1, d2, and d3. d0 and d3 are required by speci?cation, and d1 and d2 are optional. d0 is the maximum powered state, and d3 is the minimum powered state. power state d3 is further categorized as d3hot or d3cold. a function that is powered off is said to be in the d3cold power state. the power states for the scsi function are independently controlled through two power state bits that are located in the pci con?guration space register 0x44. the bits are encoded as: power states d1 and d2 are not discussed because they have not been implemented as a new feature. the power states C d0 and d3 C are described below in conjunction with each scsi function. power state actions are separate for each function. 2.5.1 power state d0 power state d0 is the maximum power state and is the power-up default state for each function. 2.5.2 power state d3 power state d3 is the minimum power state, which includes subsettings called d3hot and d3cold. the devices are considered to be in power state d3cold when power is removed from them. d3cold can transition to d0 by applying vcc and resetting the device. d3hot allows the device to transition to d0 using software. to obtain power reduction in d3hot, the scsi clock and the scsi clock doubler phase lock loop (pll) are disabled. furthermore, the functions soft reset is continually asserted while in power state d3, which clears all pending interrupts and 3-states the scsi bus. in addition, the functions pci command register is cleared. 00b d0 01b reserved 10b reserved 11b d3 LSI53C825A/825ae pci to scsi i/o processor 3-1 chapter 3 signal descriptions this chapter presents the LSI53C825A pin con?guration and signal de?nitions using tables and illustrations. figure 3.1 through figure 3.2 are the pin diagrams for all versions of the LSI53C825A and figure 3.3 is the functional signal grouping. the pin de?nitions are presented in table 3.1 through table 3.10 . the LSI53C825A is a pin-for-pin replacement for the lsi53c825. this chapter is divided into the following sections: section 3.1, pci bus interface signals section 3.2, mad bus programming 3-2 signal descriptions figure 3.1 LSI53C825A pin diagram c_be3/ ad23 ad22 v dd-i ad18 c_be2/ irdy/ v ss stop/ par/ v ss ad15 ad11 v ss ad8 c_be0/ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 36 37 38 39 40 ad17 v ss v ss v dd-i quad flat pack 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 idsel v ss ad20 v ss ad16 frame/ v dd-i v ss c_be1/ ad13 ad12 ad9 ad21 ad19 trdy/ devsel/ perr/ ad14 ad10 ad7 sdir7 v dd sd13/ sd15/ sd1/ sd4/ v ss-s sd6/ v ss-s srst/ ssel/ v ss-s sd9/ v dd sdir8 sdir9 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 85 84 83 82 81 v ss-s sd3/ si_o/ v ss-s 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 sdirp0 sd12/ v ss-s sd0/ sd2/ sd5/ satn/ sbsy/ smsg/ sreq/ sd8/ sd11/ sd14/ sdp1/ sd7/ sdp0/ sack/ sc_d/ sd10/ sdir10 ad6 ad5 v dd-i v ss v dd-c v ss-c testin mac/_testout mad4 mad2 mad0 gpio2_mas2/ v dd rstdir bsydir v ss irq/ gpio1_master/ gpio4 tgs v ss ad4 ad2 ad0 gpio0_fetch/ sclk mad5 v dd mad1 gpio3 diffsens seldir ad3 ad1 mad7 mad6 mad3 v ss igs v ss sdir3 sdir2 sdirp1 v ss sdir12 mas1/ big_lit/ clk v ss-c gnt/ v dd-c ad31 ad30 ad28 121 123 125 127 129 131 133 135 137 139 141 143 144 145 146 147 148 150 152 154 156 158 sdir5 mwe/ mce/ v ss ad29 ad27 ad26 ad24 160 ad25 122 124 126 128 130 132 134 136 138 140 142 149 151 153 155 157 159 sdir6 sdir4 sdir0 sdir15 sdir13 v dd moe/ rst/ sdir1 v dd sdir14 mas0/ serr/ req/ v dd-i v ss 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 76 77 78 79 80 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 scsi i/o processor 160-pin sdir11 (top view) note: the decoupling capacitor arrangement shown above is recommended to maximize the bene?ts of the internal split ground system. capacitor values between 0.01 and 0.1 m f should provide adequate noise isolation. because of the number of high current drivers on the LSI53C825A, a multilayer pc board with power and ground planes is required. 3-3 figure 3.2 LSI53C825Aj pin diagram the pci/scsi pin de?nitions are organized into the following functional groups: system, address/data, interface control, arbitration, error reporting, scsi, and optional interface. a slash (/) at the end of the signal name indicates that the active state occurs when the signal is at a low voltage. when the slash is absent, the signal is active at a high voltage. c_be3/ ad23 ad22 v dd-i ad18 c_be2/ irdy/ v ss stop/ par/ v ss ad15 ad11 v ss ad8 c_be0/ 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 36 37 38 39 40 ad17 v ss v ss v dd-i quad flat pack 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 idsel v ss ad20 v ss ad16 frame/ v dd-i v ss c_be1/ ad13 ad12 ad9 ad21 ad19 trdy/ devsel/ perr/ ad14 ad10 ad7 sdir7 v dd sd13/ sd15/ sd1/ sd4/ v ss-s sd6/ v ss-s srst/ ssel/ v ss-s sd9/ v dd sdir8 sdir9 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 85 84 83 82 81 v ss-s sd3/ si_o/ v ss-s 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 89 87 sdirp0 sd12/ v ss-s sd0/ sd2/ sd5/ satn/ sbsy/ smsg/ sreq/ sd8/ sd11/ sd14/ sdp1/ sd7/ sdp0/ sack/ sc_d/ sd10/ sdir10 ad6 ad5 v dd-i v ss v dd-c v ss-c tms tdo mad4 mad2 mad0 gpio2_mas2/ v dd rstdir bsydir v ss irq/ gpio1_master/ gpio4 tgs v ss ad4 ad2 ad0 gpio0_fetch/ sclk mad5 v dd mad1 gpio3 diffsens seldir ad3 ad1 mad7 mad6 mad3 v ss igs v ss sdir3 sdir2 tck v ss sdir12 mas1/ tdi clk v ss-c gnt/ v dd-c ad31 ad30 ad28 121 123 125 127 129 131 133 135 137 139 141 143 144 145 146 147 148 150 152 154 156 158 sdir5 mwe/ mce/ v ss ad29 ad27 ad26 ad24 160 ad25 122 124 126 128 130 132 134 136 138 140 142 149 151 153 155 157 159 sdir6 sdir4 sdir0 sdir15 sdir13 v dd moe/ rst/ sdir1 v dd sdir14 mas0/ serr/ req/ v dd-i v ss 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 76 77 78 79 80 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 scsi i/o processor 160-pin sdir11 (top view) 3-4 signal descriptions there are four signal type de?nitions: i input, a standard input-only signal. o output, a standard output driver (typically a totem pole output). t/s 3-state, a bidirectional, 3-state input/output signal. s/t/s sustained 3-state, an active low 3-state signal owned and driven by one and only one agent at a time. table 3.1 LSI53C825A, LSI53C825Aj, LSI53C825Ae, and LSI53C825Aje power and ground pins symbol pin no. description v ss 4, 10, 14, 18, 23, 27, 31, 37, 42, 48, 69, 79, 123, 133, 152, 158 ground to the pci i/o pins v dd 8, 33, 45, 63, 74, 84, 118, 128, 138 , 155 power supplies to the standard i/o pins v dd-i 1 1. these pins can accept a vdd source of 3.3 or 5 volts. all other vdd pins must be supplied 5 volts. 8, 21, 33, 45, 155 v dd pad for pci i/o pins v ss -s 88, 93, 99, 104, 109, 114 ground to the scsi bus i/o pins v ss -c 55, 146 ground to the internal logic core v dd -c 51, 149 power supplies to the internal logic core 3-5 figure 3.3 is the functional signal grouping for the LSI53C825A. figure 3.3 LSI53C825A functional signal grouping LSI53C825A clk rst ad[31:0] c_be/[3:0] pa r frame/ trdy/ irdy/ stop/ devsel/ idsel req/ gnt/ serr/ perr/ tgs gpio[4:3] gpio0_fetch/ gpio1_master/ mac/_testout irq/ big_lit/ diffsens gpio2_mas2/ mwe/ mce/ moe/ mas0/ system address and data interface control arbitration error reporting scsi mas1/ bsydir rstdir seldir igs sdirp[1:0] sdir[15:0] sclk sd[15:0] sdp[1:0] sctrl additional mad[7:0] testin/ device local memory bus and control interface 3-6 signal descriptions 3.1 pci bus interface signals the pci bus interface signals section contains tables describing the signals for the following signal groups: system signals , address and data signals , interface control signals , arbitration signals , error reporting signals , scsi bus interface signals , additional interface signals , external memory interface signals , and jtag signals. 3.1.1 system signals table 3.2 describes the signals for the system signals group: table 3.2 system signals name pin no. type description clk 145 i clock provides timing for all transactions on the pci bus and is an input to every pci device. all other pci signals are sampled on the rising edge of clk, and other timing parameters are de?ned with respect to this edge. this clock can optionally be used as the scsi core clock; however, the LSI53C825A is not able to achieve fast scsi transfer rates. rst/ 144 i reset forces the pci sequencer of each device to a known state. all t/s and s/t/s signals are forced to a high impedance state, and all internal logic is reset. the rst/ input is synchronized internally to the rising edge of clk. the clk input must be active while rst/ is active to properly reset the device. pci bus interface signals 3-7 3.1.2 address and data signals table 3.3 describes the signals for the address and data signals group: table 3.3 address and data signals name pin no. type description ad[31:0] 150, 151, 153, 154, 156, 157, 159, 160, 3, 5, 6, 7, 9, 11, 12, 13, 28, 29, 30, 32, 34, 35, 36, 38, 40, 41, 43, 44, 46, 47, 49, 50 t/s physical longword address and data are multiplexed on the same pci pins. during the ?rst clock of a transaction, ad[31:0] contain a physical address. during subsequent clocks, ad[31:0] contain data. a bus transaction consists of an address phase, followed by one or more data phases. pci supports both read and write bursts. ad[7:0] de?ne the least signi?cant byte, and ad[31:24] de?ne the most signi?cant byte. c_be[3:0]/ 1, 15, 26, 39 t/s bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c_be[3:0]/ de?ne the bus command. during the data phase, c_be[3:0]/ are used as byte enables. the byte enables determine which byte lanes carry meaningful data. c_be(0)/ applies to byte 0, and c_be(3)/ to byte 3. par 25 t/s parity is the even parity bit that protects the ad[31:0] and c_be[3:0]/ lines. during address phase, both the address and command bits are covered. during data phase, both data and byte enables are covered. 3-8 signal descriptions 3.1.3 interface control signals table 3.4 describes the signals for the interface control signals group: table 3.4 interface control signals name pin no. type description frame/ 16 s/t/s cycle frame is driven by the current master to indicate the beginning and duration of an access. frame/ is asserted to indicate a bus transaction is beginning. while frame/ is asserted, data transfers continue. when frame/ is deasserted, the transaction is in the ?nal data phase or the bus is idle. trdy/ 19 s/t/s target ready indicates the target agents (selected devices) ability to complete the current data phase of the transaction. trdy/ is used with irdy/. a data phase is completed on any clock when both trdy/ and irdy/ are sampled asserted. during a read, trdy/ indicates that valid data is present on ad[31:0]. during a write, it indicates the target is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. irdy/ 17 s/t/s initiator ready indicates the initiating agents (bus masters) ability to complete the current data phase of the transaction. this signal is used with trdy/. a data phase is completed on any clock when both irdy/ and trdy/ are sampled asserted. during a write, irdy/ indicates that valid data is present on ad[31:0]. during a read, it indicates the master is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. stop/ 22 s/t/s stop indicates that the selected target is requesting the master to stop the current transaction. devsel/ 20 s/t/s device select indicates that the driving device has decoded its address as the target of the current access. as an input, it indicates to a master whether any device on the bus has been selected. idsel 2 i initialization device select is used as a chip select in place of the upper 24 address lines during con?guration read and write transactions. pci bus interface signals 3-9 3.1.4 arbitration signals table 3.5 describes the signals for the arbitration signals group: 3.1.5 error reporting signals table 3.6 describes the signals for the error reporting signals group: table 3.5 arbitration signals name pin no. type description req/ 148 o request indicates to the arbiter that this agent desires use of the pci bus. this is a point-to-point signal. every master has its own req/. gnt/ 147 i grant indicates to the agent that access to the pci bus has been granted. this is a point-to-point signal. every master has its own gnt/. table 3.6 error reporting signals name pin no. type description perr/ 24 s/t/s parity error may be pulsed active by an agent that detects a data parity error. perr/ can be used by any agent to signal data corruptions. serr/ 143 o system error is an open drain output pin used to report address parity errors. on detection of a perr/ pulse, the central resource may generate a nonmaskable interrupt to the host cpu, which often implies the system is unable to continue operation once error processing is complete. 3-10 signal descriptions 3.1.6 scsi bus interface signals table 3.7 describes the scsi bus interface signals group: table 3.7 scsi bus interface signals name pin no. type description sclk 56 i sclk is used to derive all scsi-related timings. the speed of this clock is determined by the applications requirements; in some applications sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low. sd[15:0]/, sdp[1:0]/ 113, 115, 116, 117, 85, 86, 87, 89, 102, 103, 105, 106, 107, 108, 110, 111, 112, 101 i/o scsi data includes the following data lines and parity signals: sd[15:0]/ (16-bit scsi data bus), and sdp[1:0]/ (scsi data parity bits). sctrl/ 92, 90, 95, 91, 97, 98, 100, 96, 94 i/o scsi control includes the following signals: sc_d/ scsi phase line, command/data si_o/ scsi phase line, input/output smsg/ scsi phase line, message sreq/ data handshake signal from target device sack/ data handshake signal from initiator device sbsy/ scsi bus arbitration signal, busy satn/ scsi attention, the initiator is requesting a message out phase srst/ scsi bus reset ssel/ scsi bus arbitration signal, select device sdir[15:0] 131, 132, 134, 135, 80, 81, 82, 83, 120, 121, 122, 124, 125, 126, 127, 129 o driver direction control for scsi data lines. sdirp[1:0] (sdipr1 not available on LSI53C825Aj) 130, 119 o driver direction control for scsi parity signals. in the LSI53C825Aj, this pin is replaced by the tck jtag signal. if the device is used in a wide differential system, use the sdirp0 pin to control the direction of the differential transceiver for both the sp0 and sp1 signals. the sdirp0 signal is capable of driving both direction inputs from a transceiver. seldir 76 o driver enable control for scsi sel/ signal. pci bus interface signals 3-11 3.1.7 additional interface signals table 3.8 describes the signals for the additional interface signals group: rstdir 77 o driver enable control for scsi rst/ signal. bsydir 78 o driver enable control for scsi bsy/ signal. igs 75 o direction control for initiator driver group. tgs 73 o direction control for target driver group. table 3.7 scsi bus interface signals (cont.) name pin no. type description table 3.8 additional interface signals name pin no. type description testin (not available on LSI53C825Aj) 57, na i test in . when this pin is driven low, the LSI53C825A connects all inputs and outputs to an and tree. the scsi control signals and data lines are not connected to the and tree. the output of the and tree is connected to the test out pin. this allows manufacturers to verify chip connectivity and determine exactly which pins are not properly attached. when the testin pin is driven low, internal pull-ups are enabled on all input, output, and bidirectional pins, all outputs and bidirectional signals are 3-stated, and the mac/_testout pin is enabled. connectivity can be tested by driving one of the LSI53C825A pins low. the mac/_testout pin should respond by also driving low. gpio0_ fetch/ 53/70/n5 i/o general purpose i/o pin. optionally, when driven low, this pin indicates that the next bus request will be for an opcode fetch. this pin powers up as a general purpose input. this pin has two speci?c purposes in the lsi logic sdms software. sdms software uses it to toggle scsi device leds, turning on the led whenever the LSI53C825A is on the scsi bus. sdms software drives this pin low to turn on the led, or drives it high to turn off the led. this signal can also be used as data i/o for serial eeprom access. in this case it is used with the gpio0 pin, which serves as a clock, and the pin can be controlled from pci con?guration register 0x35 or observed from the general purpose (gpreg) register, at address 0x07. 3-12 signal descriptions gpio1_ master/ 54 i/o general purpose i/o pin. optionally, when driven low, indicates that the LSI53C825A is bus master. this pin powers up as a general purpose input. lsi logic sdms software supports use of this signal in serial eeprom applications, when enabled, in combination with the gpio0 pin. when this signal is used as a clock for serial eeprom access, the gpio1 pin serves as data, and the pin is controlled from pci con?guration register 0x35. gpio[4:3] 71, 70 i/o general purpose i/o pins. gpio4 powers up as an output. it can be used as the enable line for v pp , the 12 volt power supply to the external ?ash memory interface. gpio3 powers up as an input. lsi logic sdms software uses gpio3 to detect a differential board. if the pin is pulled low externally, the board will be con?gured by sdms software as a differential board. if it is pulled high or left ?oating, sdms software will con?gure it as a se board. the lsi logic pci to scsi host adapters use the gpio4 pin in the process of ?ashing a new sdms software rom. diffsens 72 i the differential sense pin detects the presence of a se device on a differential system. when external differential transceivers are used and a zero is detected on this pin, all chip scsi outputs will be 3-stated to avoid damage to the transceivers. this pin should be tied high during se operation. the normal value of this pin is 1. mac/_ testout (not available on LSI53C825Aj) 58, na t/s memory access control . this pin can be programmed to indicate local or system memory accesses (non-pci applications). it is also used to test the connectivity of the LSI53C825A signals using an and tree scheme. the mac/_testout pin is only driven as the test out function when the testin/ pin is driven low. irq/ 52/69/ m5 o interrupt . this signal, when asserted low, indicates that an interrupting condition has occurred and that service is required from the host cpu. the output drive of this pin is programmed as either open drain with an internal weak pull-up or, optionally, as a totem pole driver. refer to the description of dma control (dcntl) register, bit 3, for additional information. table 3.8 additional interface signals (cont.) name pin no. type description pci bus interface signals 3-13 big_lit/ (not available on LSI53C825Aj) 142, na i big_little endian select . when this pin is driven low, the LSI53C825A routes the ?rst byte of an aligned scsi to pci transfer to byte lane zero of the pci bus and subsequent bytes received are routed to ascending lanes. an aligned pci to scsi transfer routes pci byte lane zero onto the scsi bus ?rst, and transfers ascending byte lanes in order. when this pin is driven high, the LSI53C825A routes the ?rst byte of an aligned scsi to pci transfer to byte lane three of the pci bus and subsequent bytes received are routed to descending lanes. an aligned pci to scsi transfer routes pci byte lane three onto the scsi bus ?rst and transfer descending byte lanes in order. this mode of operation also applies to the external memory interface. when this pin is driven in little endian mode and the chip is performing a read from external memory, the byte of data accessed at location 0x00000 is routed to pci byte lane zero and the data accessed at location 0x00003 is routed to pci byte lane three. when the chip is performing a write to ?ash memory, pci byte lane zero is routed to location 0x00000 and ascending byte lanes are routed to subsequent memory locations. when this pin is driven in big endian mode and the chip is performing a read from external memory, the byte of data accessed at location 0x00000 is routed to pci byte lane three and the data accessed at location 0x00003 is routed to byte lane zero. when the chip is performing a write to ?ash memory, pci byte lane three is routed to location 0x00000 and descending byte lanes is routed to subsequent memory locations. table 3.8 additional interface signals (cont.) name pin no. type description 3-14 signal descriptions 3.1.8 external memory interface signals table 3.9 describes the signals for the external memory interface signals group: table 3.9 external memory interface signals name pin no. type description mas0/ 137/179/a8 o memory address strobe 0 . this pin is used to latch in the least signi?cant address byte of an external eprom or ?ash memory. since the LSI53C825A moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?ip-?ops which are used to assemble up to a 20-bit address for the external memory. mas1/ 136/178/b8 o memory address strobe 1 . this pin is used to latch in the address byte corresponding to address bits [15:8] of an external eprom or ?ash memory. since the LSI53C825A moves addresses eight bits at a time, this pin connects to the clock of an external bank of ?ip-?ops which assemble up to a 20-bit address for the external memory. mad[7:0] 59, 60, 61, 62, 64, 65, 66, 67 i/o memory address/data bus . this bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external eprom or ?ash memory. this bus will put out the most signi?cant byte ?rst and ?nish with the least signi?cant bits. it is also used to write data to a ?ash memory or read data into the chip from external eprom/?ash memory. see section 3.2, mad bus programming, for more details. mwe/ 139/181/c7 o memory write enable . this pin is used as a write enable signal to an external ?ash memory. moe/ 140/182/b7 o memory output enable . this pin is used as an output enable signal to an external eprom or ?ash memory during read operations. mce/ 141/183/a7 o memory chip enable . this pin is used as a chip enable signal to an external eprom or ?ash memory device. gpio2_ mas2/ 68/87/j8 i/o general purpose i/o pin. optionally, this pin is used as a memory address strobe 2 if an external memory with more than 16 bits of addressing is speci?ed by the pull-down resistors at power-up and bit 0 in the expansion rom base address register is set. mad bus programming 3-15 3.1.9 jtag signals table 3.10 describes the signals for the jtag signals group: 3.2 mad bus programming the mad[7:0] pins, in addition to serving as the address/data bus for the local memory interface, are also used to program power-up options for the chip. a particular option is programmed by connecting a 4.7 k w resistor between the appropriate mad(x) pin and vss. the pull-down resistors require that hc or hct external components are used for a memory interface. mad[7] C has no functionality. do not place a pull-down resistor on this pin. mad[6] C subsystem data con?guration. please refer to the table 3.11 for the different con?gurations. mad[5] C scripts ram disable. connecting a 4.7 k w resistor between mad[5] and vss disables scripts ram. mad[4] C subsystem data con?guration. please refer to the table 3.11 and table 3.12 below for the different con?gurations. table 3.10 jtag signals (LSI53C825Aj, LSI53C825Aje only) name pin no. type description tck 130/130 C test clock pin for jtag boundary scan. tms 57/57 C test mode select pin for jtag boundary scan. tdi 142/142 C test data in pin for jtag boundary scan. tdo 58/58 C test data out pin for jtag boundary scan. 3-16 signal descriptions mad[3:1] C used to set the size of the external expansion rom device attached. encoding for these pins are listed in table 3.13 . table 3.11 subsystem data con?guration table for the LSI53C825Ae (pci rev id 0x26) mode mad pins offset normal 4-hi, 6-hi read/write 4-hi, 6-lo reserved 4-low, 6-hi lsi logic 4-low, 6-lo vendor id 0x00 0x1000 0x1000 C 0x1000 device id 0x02 0x000f 0x000f C 0x000f subsystem vendor id 0x2c 0x1000 0x0000 C 0x0000 subsystem id 0x2e 0x1000 0x0000 C 0x0000 table 3.12 subsystem data con?guration table for the LSI53C825A (pci rev id 0x14) revision g only 1 1. the chip revisions before revision g of the LSI53C825A (pci rev id 0x14) do not support different subsystem data con?gurations. the subsystem id (ssid) and subsystem vendor id (ssvid) registers are hardwired to zero values. mode mad pins offset normal 4-hi, 6-hi read/write 4-hi, 6-lo reserved 4-low, 6-hi lsi logic 4-low, 6-lo vendor id 0x00 0x1000 0x1000 C 0x1000 device id 0x02 0x000f 0x000f C 0x000f subsystem vendor id 0x2c 0x0000 0x0000 C 0x1000 subsystem id 0x2e 0x0000 0x0000 C 0x1000 mad bus programming 3-17 mad[0 ] C the slow rom pin. when pulled down, it enables two extra clock cycles of data access time to allow use of slower memory devices. note: all mad pins have internal pull-up resistors. table 3.13 external memory support mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present 3-18 signal descriptions LSI53C825A/825ae pci to scsi i/o processor 4-1 chapter 4 registers this chapter describes all LSI53C825A registers and is divided into the following sections: section 4.1, con?guration registers section 4.2, operating registers 4.1 con?guration registers the con?guration registers are accessible only by the system bios during pci con?guration cycles, and they are not available to the user at any time. these registers can be accessed by scripts or the host processor. the lower 128 bytes hold con?guration data while the upper 128 bytes hold the LSI53C825A operating registers, which are described in chapter 5, scsi scripts instruction set. please note that the information about lower and upper bytes only applies to the LSI53C825A and not the LSI53C825Ae. note: the con?guration register descriptions provide general information only, to indicate which pci con?guration addresses are supported in the LSI53C825A. for detailed information, refer to the pci speci?cation. table 4.1 shows the pci con?guration registers implemented by the LSI53C825A/825ae. all pci-compliant devices, such as the LSI53C825A, must support the vendor id , device id , command , and status registers. support of other pci-compliant registers is optional. in the LSI53C825A, registers that are not supported are not writable and return all zeros when read. only those registers and bits that are currently supported by the LSI53C825A are described in this chapter. reserved bits should not be accessed. 4-2 registers table 4.1 pci con?guration register map 31 16 15 0 device id vendor id 0x00 status command 0x04 class code revision id 0x08 not supported header type latency timer cache line size 0x0c base address zero (i/o) 1 scsi operating registers 1. i/o base is supported. 0x10 base address one (memory) 2 scsi operating registers 2. memory base is supported. 0x14 base address two (memory) scripts ram 3 3. this register powers up enabled and can be disabled by pull-down resistors on the mad5 pin. 0x18 not supported 0x1c not supported 0x20 not supported 0x24 reserved 0x28 subsystem id (ssid) subsystem vendor id (ssvid) 0x2c expansion rom base address 4 4. if expansion memory is enabled through pull-down resistors on the mad[7:0] bus. note: addresses 0x40C7f are not de?ned for the LSI53C825A. addresses 0x48C7f are not de?ned for the LSI53C825Ae. all unsupported registers are not writable and return all zeros when read. reserved registers also return zeros when read. 0x30 reserved capability pointer 0x34 reserved 0x38 max_lat min_gnt interrupt pin interrupt line 0x3c power management capabilities next item pointer capability id 0x40 data bridge support extension power management control/status 0x44 con?guration registers 4-3 register: 0x00 vendor id read only vid vendor id [15:0] this ?eld identi?es the manufacturer of the device. the vendor id is 0x1000. register: 0x02 device id read only did device id [15:0] this ?eld identi?es the particular device. the LSI53C825A device id is 0x0003. this value is the same as in the lsi53c825, since the LSI53C825A is a drop in replacement. the devices are uniquely identi?ed in the upper nibble of the revision id register. register: 0x04 command read/write the command register provides coarse control over a devices ability to generate and respond to pci cycles. when a zero is written to this register, the LSI53C825A is logically disconnected from the pci bus for all accesses except con?guration accesses. in the LSI53C825A, bits 3 through 5 and bit 7 and 9 are not implemented. bits 10 through 15 are reserved. 15 0 vid 1111000000000000 15 0 did 0000000000000000 15 9 8 7 6 5 4 3 2 1 0 rse r eper r wie r ebm ems eis 0 0 0 0 0 0 00 00 00 00 00 4-4 registers r reserved [15:9] se serr/enable 8 this bit enables the serr/ driver. serr/ is disabled when this bit is clear. the default value of this bit is zero. this bit and bit 6 must be set to report address parity errors. r reserved 7 eper enable parity error response 6 this bit allows the LSI53C825A to detect parity errors on the pci bus and report these errors to the system. only data parity checking is enabled. the LSI53C825A always generates parity for the pci bus. r reserved 5 wie write and invalidate mode 4 this bit, when set, causes memory write and invalidate cycles to be issued on the pci bus after certain conditions have been met. for more information on these conditions, refer to section 2.1.2.7, memory write and invalidate command. to enable write and invalidate mode, bit 10 in the chip test three (ctest3) register (operating register set) must also be set. r reserved 3 ebm enable bus mastering 2 this bit controls the ability of the LSI53C825A to act as a master on the pci bus. a value of zero disables the device from generating pci bus master accesses. a value of one allows the lsi53825a to behave as a bus master. the LSI53C825A must be a bus master in order to fetch scripts instructions and transfer data. ems enable memory space 1 this bit controls the ability of the LSI53C825A to respond to memory space accesses. a value of zero disables the device response. a value of one allows the LSI53C825A to respond to memory space accesses at the address speci?ed by base address one (memory) . con?guration registers 4-5 eis enable i/o space 0 this bit controls the LSI53C825A response to i/o space accesses. a value of zero disables the response. a value of one allows the LSI53C825A to respond to i/o space accesses at the address speci?ed in base address one (memory) . register: 0x06 status read/write the status register is used to record status information for pci bus related events. in the LSI53C825A, bits 0 through 4 are reserved and bits 5, 6, 7, and 11 are not implemented by the LSI53C825A. reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is reset whenever the register is written, and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. dpe detected parity error (from slave) 15 this bit is set by the LSI53C825A whenever it detects a data parity error, even if parity error handling is disabled. sse signaled system error 14 this bit is set whenever a device asserts the serr/ signal. rma received master abort (from master) 13 a master device should set this bit whenever its transaction (except for special cycle) is terminated with master abort. rta received target abort (from master) 12 a master device should set this bit whenever its transaction is terminated with a target abort. 15 14 13 12 11 10 9 8 7 5 4 3 0 dpe sse rma rta r dt[1:0] dpr rnc r 0000 0000 0 0 01 0 0 0 0 4-6 registers r reserved 11 dt[1:0] devsel/ timing [10:9] these bits encode the timing of devsel/. these are encoded as: these bits are read only and should indicate the slowest time that a device asserts devsel/ for any bus command except con?guration read and con?guration write. in the LSI53C825A, 0b01 is supported. dpr data parity reported 8 this bit is set when the following three conditions are met: the bus agent asserted perr/ itself or observed perr/ asserted and; the agent setting this bit acted as the bus master for the operation in which the error occurred and; the parity error response bit in the command register is set. r reserved [7:5] nc new capabilities (nc) 4 this bit is set to indicate a list of extended capabilities such as pci power management. this bit is read only, and applies to the LSI53C825Ae only. r reserved [3:0] 0b00 fast 0b01 medium 0b10 slow 0b11 reserved con?guration registers 4-7 register: 0x08 revision id read only rid revision id [7:0] this register speci?es a device speci?c revision identi?er. for revision a of the LSI53C825Ae, the value of this register is 0x26. register: 0x09 class code read only cc[23:0] class code [23:0] this register is used to identify the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?es a speci?c register-level programming interface. the value of this register is 0x010000, which identi?es a scsi controller. 7 0 rid LSI53C825Ae 00100110 LSI53C825A 00010100 23 0 cc[23:0] 000011110000000000000000 4-8 registers register: 0x0c cache line size read/write cls cache line size [7:0] this register speci?es the system cache line size in units of 32-bit words. cache mode is enabled and disabled by the cache line size enable (clse) bit, bit 7 in the dma control (dcntl) register. setting this bit causes the LSI53C825A to align to cache line boundaries before allowing any bursting, except during memory moves in which the read and write addresses are not aligned to a burst size boundary. for more information on this register, see section 2.1.3.1, support for pci cache line size register. register: 0x0d latency timer read/write lt[7:0] latency timer [7:0] the latency timer register speci?es, in units of pci bus clocks, the value of the latency timer for this pci bus master. the LSI53C825A supports this timer. all eight bits are writable, allowing latency values of 0C255 pci clocks. use the following equation to calculate an optimum latency value for the LSI53C825A: latency = 2 + (burst size * (typical wait states +1)). values greater than optimum are also acceptable. 7 0 cls 00000000 7 0 lt 00000000 con?guration registers 4-9 register: 0x0e header type read only ht[7:0] header type [7:0] this register identi?es the layout of bytes 0x10 through 0x3f in con?guration space and also whether or not the device contains multiple functions. the value of this register is 0x00. register: 0x10 base address zero (i/o) read/write barz base address register zero (i/o) [31:0] this 32-bit register has bit zero hardwired to one. bit 1 is reserved and must return a zero on all reads, and the other bits are used to map the device into i/o space. register: 0x14 base address one (memory) read/write baro base address register one [31:0] this register has bit 0 hardwired to zero. for detailed information on the operation of this register, refer to the pci speci?cation. 7 0 ht 00000000 31 0 barz xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1 31 0 baro xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 4-10 registers register: 0x18 ram base address two (memory) scripts ram read/write bart base address register two [31:0] this register holds the memory base address of the 4 kbyte internal ram. the user can read this register through the scratch register b (scratchb) register in the operating register set when bit 3 of the chip test two (ctest2) register is set. register: 0x2c subsystem vendor id (ssvid) read only ssvid subsystem vendor id [15:0] this register supports subsystem identi?cation, which has a default value of 0x1000 in the LSI53C825Ae ( section 3.2, mad bus programming ). to write to this register, connect a 4.7 k w resistor between the mad[6] pin and v ss and leave the mad[4] pin unconnected. the mad[6] and mad[4] pins have internal pull-up resistors and are sensed shortly after the deassertion of chip reset. in revisions before rev. g of the LSI53C825A, the mad[6] and mad[4] pins do not support the ssid and ssvid con?gurations, and only values of 0x0000 can be found in the subsystem data register. 31 0 bart xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 15 0 ssvid LSI53C825Ae 1111000000000000 LSI53C825A 0000000000000000 con?guration registers 4-11 register: 0x2e subsystem id (ssid) read only ssid subsystem id [15:0] this register supports subsystem identi?cation, which has a default value of 0x1000 in the LSI53C825Ae ( section 3.2, mad bus programming ). to write to this register, connect a 4.7 k w resistor between the mad[6] pin and v ss and leave the mad[4] pin unconnected. the mad[6] and mad[4] pins have internal pull-up resistors and are sensed shortly after the deassertion of chip reset. in revisions before revision g of the LSI53C825A, the mad[6] and mad[4] pins do not support the ssid and ssvid con?gurations, and only values of 0x0000 can be found in the subsystem data register. register: 0x30 expansion rom base address read/write erba expansion rom base address [31:0] this four-byte register handles the base address and size information for expansion rom. it functions exactly like the base address zero (i/o) and base address one (memory) registers, except that the encoding of the bits is different. the upper 21 bits correspond to the upper 21 bits of the expansion rom base address. 15 0 ssid LSI53C825Ae 1111000000000000 LSI53C825A 0000000000000000 31 0 erba 00000000000000000000000000000000 4-12 registers the expansion rom enable bit, bit 0, is the only bit de?ned in this register. this bit is used to control whether or not the device accepts accesses to its expansion rom. when the bit is set, address decoding is enabled, and a device can be used with or without an expansion rom depending on the system con?guration. to access the external memory interface, the memory space bit in the command register must also be set. the host system detects the size of the external memory by ?rst writing the expansion rom base address register with all ones and then reading back the register. the LSI53C825A will respond with zeros in all dont care locations. the ones in the remaining bits represent the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register, when written with ones and read back, will return ones in the upper 17 bits. register: 0x34 capability pointer read only cp capabilities pointer [7:0] this register provides an offset into the functions pci con?guration space for the location of the ?rst item in the capabilities linked list. only the LSI53C825Ae sets this register to 0x40. the capability pointer replaces the general purpose pin control register in earlier revisions of the LSI53C825A. 7 0 cp 01000000 con?guration registers 4-13 register: 0x3c interrupt line read/write il interrupt line [7:0] this register is used to communicate interrupt line routing information. post software will write the routing information into this register as it initiates and con?gures the system. the value in this register tells which input of the system interrupt controller(s) the devices interrupt pin has been connected to. values in this register are speci?ed by system architecture. register: 0x3d interrupt pin read only ip[7:0] interrupt pin [7:0] this register tells which interrupt pin the device uses. its value is set to 0x01, for the inta/ signal. register: 0x3e min_gnt read only mg min_gnt [7:0] this register is used to specify the desired settings for latency timer values. min_gnt is used to specify how long a burst period the device needs. the value speci?ed in these registers is in units of 0.25 microseconds. the lsi53c25a sets this register to 0x11. 7 0 il 00000000 7 0 ip 00000001 7 0 mg 00010001 4-14 registers register: 0x3f max_lat read only ml max_lat [7:0] this register is used to specify the desired settings for latency timer values. max_lat is used to specify how often the device needs to gain access to the pci bus. the value speci?ed in these registers is in units of 0.25 microseconds. the LSI53C825A sets this register to 0x40. register: 0x40 capability id read only cid cap_id [7:0] this register indicates the type of data structure currently being used. it is set to 0x01, indicating the power management data structure. only the LSI53C825Ae sets this register to 0x01. 7 0 ml 01000000 7 0 cid 00000001 con?guration registers 4-15 register: 0x41 next item pointer read only nip next_item_ptr [7:0] this register describes the location of the next item in the functions capability list. the default value for this register is 0x00, indicating that power management is the last capability in the linked list of extended capabilities. this register applies to the LSI53C825Ae only. register: 0x42 power management capabilities read only this register applies to the LSI53C825Ae only and indicates the power management capabilities. pmes[4:0] pme support [15:11] this ?eld is always set to 00000b because the LSI53C825Ae does not provide a pme signal. d2s d2 support 10 this device does not support the d2 power management state. d1s d1 support 9 this device does not support the d1 power management state. 7 0 nip 00000000 15 11 10 9 8 6 5 4 3 2 0 pmes[4:0] d2s d1s r dsi aps pmec ver[2:0] 0 000 0 0 0 0 0 000 0 111 4-16 registers r reserved [8:6] dsi device speci?c initialization 5 this bit is cleared to indicate that the LSI53C825A requires no special initialization before the generic class device driver is able to use it. aps auxiliary power source 4 because the device does not provide a pme signal, this bit always returns a 0. this indicates that no auxiliary power source is required to support the pme signal in the d3cold power management state. pmec pme clock 3 this bit always returns a zero value because the devices do not provide a pme signal. ver[2:0] version [2:0] this ?eld is set of 001b to indicate that the device complies with revision 1.0 of the pci power management interface speci?cation. register: 0x44 power management control/status read write this register applies to the LSI53C825Ae only and indicates the power management control and status descriptions. pst pme status 15 the LSI53C825A always returns a zero for this bit, indicating that pme signal generation is not supported from d3cold. dscl data scale [14:13] the LSI53C825A does not support the data register. therefore these two bits are always set to 00b. dslt data select [12:9] this device does not support the data register. therefore these four bits are always set to 0000b. 15 14 13 12 9 8 7 2 1 0 pst dscl dslt pen r pws 00000000 0 0 0 0 0 000 con?guration registers 4-17 pen pme enable 8 the LSI53C825A always returns a zero for this bit to indicate that pme assertion is disabled. r reserved [7:2] pws power state [1:0] bits [1:0] are used to determine the current power state for the LSI53C825A. they are used to place the LSI53C825A in a new power state. power states are de?ned as: register: 0x46 bridge support extensions (pmcsr_bse) read only bse[7:0] bridge support extensions [7:0] this register applies to the LSI53C825A only and can support pci bridge speci?c functionality, if required. the default value always returns 0x00. register: 0x47 data read only data[7:0] data [7:0] this register applies to the LSI53C825Ae only and provides an optional mechanism for the function to report state dependent operating data. the LSI53C825Ae returns 0x00 as the default value. 0b00 d0 0b01 reserved 0b10 reserved 0b11 d3 hot 7 0 bse 00000000 7 0 data 00000000 4-18 registers 4.2 operating registers this section contains descriptions of all LSI53C825A operating registers. table 4.2 , the register map, lists registers by operating and con?guration addresses. the terms set and assert are used to refer to bits that are programmed to a binary one. similarly, the terms deassert, clear, and reset are used to refer to bits that are programmed to a binary zero. any bits marked as reserved should always be written to zero; mask all information read from them. reserved bit functions may be changed at any time. unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. the bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. note: the only register that the host cpu can access while the LSI53C825A is executing scripts is the interrupt status (istat) register; attempts to access other registers will interfere with the operation of the chip. however, all operating registers are accessible with scripts. all read data is synchronized and stable when presented to the pci bus. the LSI53C825A cannot fetch scripts instructions from the operating register space. instructions must be fetched from system memory or the internal scripts ram. operating registers 4-19 table 4.2 LSI53C825A register map 31 16 15 0 scntl3 scntl2 scntl1 scntl0 0x00 gpreg sdid sxfer scid 0x04 sbcl ssid socl sfbr 0x08 sstat2 sstat1 sstat0 dstat 0x0c dsa 0x10 reserved istat 0x14 ctest3 ctest2 ctest1 reserved 0x18 temp 0x1c ctest6 ctest5 ctest4 dfifo 0x20 dcmd dbc 0x24 dnad 0x28 dsp 0x2c dsps 0x30 scratch a 0x34 dcntl sbr dien dmode 0x38 adder 0x3c sist1 sist0 sien1 sien0 0x40 gpcntl macntl swide slpar 0x44 respid1 respid0 stime1 stime0 0x48 stest3 stest2 stest1 stest0 0x4c reserved sidl 0x50 reserved sodl 0x54 reserved sbdl 0x58 scratch b 0x5c scratch c 0x60 scratch d 0x64 scratch e 0x68 scratch f 0x6c scratch g 0x70 scratch h 0x74 scratch i 0x78 scratch j 0x7c 4-20 registers register: 0x00 (0x80) scsi control zero (scntl0) read/write arb[1:0] arbitration mode bits 1 and 0 [7:6] simple arbitration 1. the LSI53C825A waits for a bus free condition to occur. 2. it asserts sbsy/ and its scsi id (contained in the scsi chip id (scid) register) onto the scsi bus. if the ssel/ signal is asserted by another scsi device, the LSI53C825A deasserts sbsy/, deasserts its id, and sets the lost arbitration bit (bit 3) in the scsi status zero (sstat0) register. 3. after an arbitration delay, the cpu should read the scsi bus data lines (sbdl) register to check if a higher priority scsi id is present. if no higher priority id bit is set, and the lost arbitration bit is not set, the LSI53C825A has won arbitration. 4. once the LSI53C825A has won arbitration, ssel/ must be asserted using the scsi output control latch (socl) for a bus clear plus a bus settle delay (1.2 m s) before a low level selection can be performed. 76543210 arb[1:0] start watn epc r aap trg 11000 x00 arb1 arb0 arbitration mode 0 0 simple arbitration 0 1 reserved 1 0 reserved 1 1 full arbitration, selection/reselection operating registers 4-21 full arbitration, selection/reselection 1. the LSI53C825A waits for a bus free condition. 2. it asserts sbsy/ and its scsi id (the highest priority id stored in the scsi chip id (scid) register) onto the scsi bus. 3. if the ssel/ signal is asserted by another scsi device or if the LSI53C825A detects a higher priority id, the LSI53C825A deasserts bsy, deasserts its id, and waits until the next bus free state to try arbitration again. 4. the LSI53C825A repeats arbitration until it wins control of the scsi bus. when it has won, the won arbitration bit is set in the scsi status zero (sstat0) register, bit 2. 5. the LSI53C825A performs selection by asserting the following onto the scsi bus: ssel/, the targets id (stored in the scsi destination id (sdid) register), and the LSI53C825A id (stored in the scsi chip id (scid) register). 6. after a selection is complete, the function complete bit is set in the scsi interrupt status zero (sist0) register, bit 6. 7. if a selection time-out occurs, the selection time-out bit is set in the scsi interrupt status one (sist1) register, bit 2. start start sequence 5 when this bit is set, the LSI53C825A starts the arbitration sequence indicated by the arbitration mode bits. the start sequence bit is accessed directly in low level mode; during scsi scripts operations, this bit is controlled by the scripts processor. an arbitration sequence should not be started if the connected (con) bit in the scsi control one (scntl1) register, bit 4, indicates that the LSI53C825A is already connected to the scsi bus. this bit is automatically cleared when the arbitration sequence is complete. if a sequence aborts, check bit 4 in the scsi control one (scntl1) register to verify that the LSI53C825A did not connect to the scsi bus. 4-22 registers watn select with satn/ on a start sequence 4 when this bit is set and the LSI53C825A is in the initiator mode, the satn/ signal is asserted during LSI53C825A selection of a scsi target device. this is to inform the target that the LSI53C825A has a message to send. if a selection time-out occurs while attempting to select a target device, satn/ deasserts at the same time ssel/ deasserts. when this bit is clear, the satn/ signal is not asserted during selection. when executing scsi scripts, this bit is controlled by the scripts processor, but it may be set manually in low level mode. epc enable parity checking 3 when this bit is set, the scsi data bus is checked for odd parity when data is received from the scsi bus in either the initiator or target mode. parity is also checked as data goes from the scsi fifo to the dma fifo. if a parity error is detected, bit 0 of the scsi interrupt status zero (sist0) register is set and an interrupt may be generated. if the LSI53C825A is operating in initiator mode and a parity error is detected, satn/ can optionally be asserted, but the transfer continues until the target changes phase. when this bit is cleared, parity errors are not reported. r reserved 2 aap assert satn/ on parity error 1 when this bit is set, the LSI53C825A automatically asserts the satn/ signal upon detection of a parity error. satn/ is only asserted in the initiator mode. the satn/ signal is asserted before deasserting sack/ during the byte transfer with the parity error. the enable parity checking bit must also be set for the LSI53C825A to assert satn/ in this manner. a parity error is detected on data received from the scsi bus. if the assert satn/ on parity error bit is cleared or the enable parity checking bit is cleared, satn/ is not automatically asserted on the scsi bus when a parity error is received. operating registers 4-23 trg target mode 0 this bit determines the default operating mode of the LSI53C825A. the user must manually set the target or initiator mode. this is done using the scripts language ( set target or clear target ). when this bit is set, the chip is a target device by default. when this bit is cleared, the LSI53C825A is an initiator device by default. caution: writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes. register: 0x01 (0x81) scsi control one (scntl1) read/write exc extra clock cycle of data setup 7 when this bit is set, an extra clock period of data setup is added to each scsi data transfer. the extra data setup time can provide additional system design margin, though it affects the scsi transfer rates. clearing this bit disables the extra clock cycle of data setup time. setting this bit only affects scsi send operations. adb assert scsi data bus 6 when this bit is set, the LSI53C825A drives the contents of the scsi output data latch (sodl) onto the scsi data bus. when the LSI53C825A is an initiator, the scsi i/o signal must be inactive to assert the sodl contents onto the scsi bus. when the LSI53C825A is a target, the scsi i/o signal must be active to assert the sodl contents onto the scsi bus. the contents of the scsi output data latch (sodl) register can be asserted at any time, even before the LSI53C825A is connected to the scsi bus. clear this bit when executing scsi scripts. it is normally used only for diagnostic testing or operation in low level mode. 76543210 exc adb dhp con rst aesp iarb sst 00000000 4-24 registers dhp disable halt on parity error or atn (target only) 5 the dhp bit is only de?ned for target mode. when this bit is cleared, the LSI53C825A halts the scsi data transfer when a parity error is detected or when the satn/ signal is asserted. if satn/ or a parity error is received in the middle of a data transfer, the LSI53C825A may transfer up to three additional bytes before halting to synchronize between internal core cells. during synchronous operation, the LSI53C825A transfers data until there are no outstanding synchronous offsets. if the LSI53C825A is receiving data, any data residing in the dma fifo is sent to memory before halting. when this bit is set, the LSI53C825A does not halt the scsi transfer when satn/ or a parity error is received. con connected 4 this bit is automatically set any time the LSI53C825A is connected to the scsi bus as an initiator or as a target. it is set after the LSI53C825A successfully completes arbitration or when it has responded to a bus initiated selection or reselection. this bit is also set after the chip wins simple arbitration when operating in low level mode. when this bit is cleared, the LSI53C825A is not connected to the scsi bus. the cpu can force a connected or disconnected condition by setting or clearing this bit. this feature is used primarily during loopback mode. rst assert scsi rst/ signal 3 setting this bit asserts the srst/ signal. the srst/ output remains asserted until this bit is cleared. the 25 m s minimum assertion time de?ned in the scsi speci?cation must be timed out by the controlling microprocessor or a scripts loop. aesp assert even scsi parity (force bad parity) 2 when this bit is set, the LSI53C825A asserts even parity. it forces a scsi parity error on each byte sent to the scsi bus from the chip. if parity checking is enabled, then the LSI53C825A checks data received for odd parity. this bit is used for diagnostic testing and is cleared for normal operation. it is useful to generate parity errors to test error handling functions. operating registers 4-25 iarb immediate arbitration 1 setting this bit causes the scsi core to immediately begin arbitration once a bus free phase is detected following an expected scsi disconnect. this bit is useful for multithreaded applications. the arb[1:0] bits in scsi control zero (scntl0) are set for full arbitration and selection before setting this bit. arbitration is retried until won. at that point, the LSI53C825A holds bsy and sel asserted, and waits for a select or reselect sequence. the immediate arbitration bit is reset automatically when the selection or reselection sequence is completed, or times out. an unexpected disconnect condition will clear iarb without attempting arbitration. see the scsi disconnect unexpected bit ( scsi control two (scntl2) , bit 7) for more information on expected versus unexpected disconnects. it is possible to abort an immediate arbitration sequence. first, set the abort bit in the interrupt status (istat) register. then one of two things eventually happens: the won arbitration bit ( scsi status zero (sstat0), bit 2) is set. in this case, the immediate arbitration bit needs to be reset. this will complete the abort sequence and disconnect the LSI53C825A from the scsi bus. if it is not acceptable to go to bus free phase immediately following the arbitration phase, a low level selection may be performed instead. the abort completes because the LSI53C825A loses arbitration. this can be detected by the immediate arbitration bit being cleared. do not use the lost arbitration bit ( scsi status zero (sstat0) , bit 3) to detect this condition. in this case take no further action. sst start scsi transfer 0 this bit is automatically set during scripts execution and should not be used. it causes the scsi core to begin a scsi transfer, including sreq/ and sack/ handshaking. the determination of whether the transfer is a send or receive is made according to the value written to the i/o bit in scsi output control latch (socl) . this bit is self-clearing. do not set it for low level operation. 4-26 registers caution: writing to this register while not connected may cause the loss of a selection/reselection by clearing the connected bit. register: 0x02 (0x82) scsi control two (scntl2) read/write sdu scsi disconnect unexpected 7 this bit is valid in the initiator mode only. when this bit is set, the scsi core is not expecting the scsi bus to enter the bus free phase. if it does, an unexpected disconnect error is generated (see the unexpected disconnect bit in the scsi interrupt status zero (sist0) register, bit 2). during normal scripts mode operation, this bit is set automatically whenever the scsi core is reselected, or successfully selects another scsi device. the sdu bit should be cleared with a register write (move 0x00 to scsi control two (scntl2) ) before the scsi core expects a disconnect to occur, normally prior to sending an abort, abort tag, bus device reset, clear queue or release recovery message, or before deasserting sack/ after receiving a disconnect command or command complete message. chm chained mode 6 this bit determines whether or not the scsi core is programmed for chained scsi mode. this bit is automatically set by the chained block move (chmov) scripts instruction and is automatically cleared by the block move scripts instruction (move). chained mode is primarily used to transfer consecutive wide data blocks. using chained mode facilitates partial receive transfers and allows correct partial send behavior. when this bit is set and a data transfer ends on an odd byte boundary, the LSI53C825A stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output data latch 76543210 sdu chm slpmd slphben wss vue0 vue1 wsr 00000000 operating registers 4-27 (sodl) register during a send operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer is completed. slpmd slpar mode 5 if this bit is clear, the scsi longitudinal parity (slpar) register functions like the lsi53c825. if this bit is set, the slpar register re?ects the high or low byte of the slpar word, depending on the state of scsi control two (scntl2) , bit 4. it also allows a seed value to be written to the scsi longitudinal parity (slpar) register. slphben slpar high byte enable 4 if this bit is clear, the low byte of the slpar word is present in the scsi longitudinal parity (slpar) register. if this bit is set, the high byte of the slpar word is present in the scsi longitudinal parity (slpar) register. wss wide scsi send 3 when read, this bit returns the value of the wide scsi send (wss) ?ag. asserting this bit clears the wss ?ag. this clearing function is self-clearing. when the wss ?ag is high following a wide scsi send operation, the scsi core is holding a byte of chain data in the scsi output data latch (sodl) register. this data becomes the ?rst low-order byte sent when married with a high-order byte during a subsequent data send transfer. performing a scsi receive operation clears this bit. also, performing any nonwide transfer clears this bit. vue0 vendor unique enhancements, bit 0 2 this bit is a read only value indicating whether the group code ?eld in the scsi instruction is standard or vendor unique. if cleared, the bit indicates standard group codes; if set, the bit indicates vendor unique group codes. the value in this bit is reloaded at the beginning of all asynchronous target receives. the default for this bit is reset. vue1 vendor unique enhancement, bit 1 1 this bit is used to disable the automatic byte count reload during block move instructions in the command phase. if this bit is cleared, the device reloads the block move byte 4-28 registers count if the ?rst byte received is one of the standard group codes. if this bit is set, the device does not reload the block move byte count, regardless of the group code. wsr wide scsi receive 0 when read, this bit returns the value of the wide scsi receive (wsr) ?ag. setting this bit clears the wsr ?ag. this clearing function is self-clearing. the wsr ?ag indicates that the scsi core received data from the scsi bus, detected a possible partial transfer at the end of a chained or nonchained block move command, and temporarily stored the high-order byte in the scsi wide residue (swide) register rather than passing the byte out the dma channel. the hardware uses the wsr status ?ag to determine what behavior must occur at the start of the next data receive transfer. when the ?ag is set, the stored data in swide may be residue data, valid data for a subsequent data transfer, or overrun data. the byte is read as normal data by starting a data receive transfer. performing a scsi send operation clears this bit. also, performing any nonwide transfer clears this bit. register: 0x03 (0x83) scsi control three (scntl3) read/write r reserved 7 scf[2:0] synchronous clock conversion factor [6:4] these bits select a factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. write these to the same value as the clock conversion factor bits below unless fast scsi operation is desired. see the scsi transfer (sxfer) register description for examples of how the scf bits are used to calculate synchronous transfer periods. see the table under the description of bits [7:5] of the scsi transfer (sxfer) register for the valid combinations. 76 432 0 r scf[2:0] ews ccf[2:0] 00000000 operating registers 4-29 note: for additional information on how the synchronous transfer rate is determine, refer to chapter 2, functional descrip- tion. ews enable wide scsi 3 when this bit is cleared, all information transfer phases are assumed to be eight bits, transmitted on sd[7:0]/ and sdp0/. when this bit is asserted, data transfers are done 16 bits at a time, with the least signi?cant byte on sd[7:0]/ and sdp0/ and the most signi?cant byte on sd[15:8]/, sdp1/. command, status, and message phases are not affected by this bit. clearing this bit also clears the wide scsi receive bit in the scsi control two (scntl2) register, which indicates the presence of a valid data byte in the scsi wide res- idue (swide) register. ccf[2:0] clock conversion factor [2:0] these bits select a factor by which the frequency of sclk is divided before being presented to the scsi core. the synchronous portion of the scsi core can be run at a different clock rate for fast scsi, using the synchronous clock conversion factor bits. the bit encoding is displayed in table 4.3 . all other combinations are reserved. table 4.3 synchronous clock conversion factor scf2 ccf2 scf1 ccf1 scf0 ccf0 factor frequency scsi clock (mhz) 0 0 0 sclk/3 50.01C75.0 0 0 1 sclk/1 16.67C25.0 0 1 0 sclk/1.5 25.01C37.5 0 1 1 sclk/2 37.51C50.0 1 0 0 sclk/3 50.01C75.0 1 0 1 reserved C 1 1 0 reserved C 1 1 1 reserved C 4-30 registers note: it is important that these bits are set to the proper values to guarantee that the LSI53C825A meets the scsi timings as de?ned by the ansi speci?cation. for additional information on how the synchronous transfer rate is determined, refer to chapter 2, functional descrip- tion. register: 0x04 (0x84) scsi chip id (scid) read/write r reserved 7 rre enable response to reselection 6 when this bit is set, the LSI53C825A is enabled to respond to bus-initiated reselection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the LSI53C825A does not automatically recon?gure itself to the initiator mode as a result of being reselected. sre enable response to selection 5 when this bit is set, the LSI53C825A is able to respond to bus-initiated selection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the LSI53C825A does not automatically recon?gure itself to target mode as a result of being selected. r reserved 4 enc[3:0] encoded chip scsi id [3:0] these bits are used to store the LSI53C825A encoded scsi id. this is the id which the chip asserts when arbitrating for the scsi bus. the ids that the LSI53C825A responds to when selected or reselected are con?gured in the response id zero (respid0) and response id one (respid1) registers. the priority of the 16 possible ids, in descending order is: 76543 0 r rre sre r enc[3:0] x00 x0000 operating registers 4-31 register: 0x05 (0x85) scsi transfer (sxfer) read/write note: when using table indirect i/o commands, bits [7:0] of this register are loaded from the i/o data structure. for additional information on how the synchronous transfer rate is determined, refer to chapter 2, functional descrip- tion. tp[2:0] scsi synchronous transfer period [7:5] these bits determine the scsi synchronous transfer period used by the LSI53C825A when sending synchronous scsi data in either the initiator or target mode. these bits control the programmable dividers in the chip. the synchronous transfer period the LSI53C825A should use when transferring scsi data is determined in the following example: highest lowest 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 754 0 tp[2:0] mo[4:0] 00000000 tp2 tp1 tp0 xferp 0004 0015 0106 0117 1008 1019 11010 11111 4-32 registers the LSI53C825A is connected to a hard disk which can transfer data at 10 mbytes/s synchronously. the LSI53C825A sclk is running at 40 mhz. the synchronous transfer period (sxferp) is found as follows: sxferp = period/sscp + extcc period = 1 ? frequency = 1 ? 10 mbytes/s = 100 ns sscp = 1 ? sscf = 1 ? 40 mhz = 25 ns (this scsi synchronous core clock is determined in scsi control three (scntl3) , bits [6:4], extcc = 1 if scsi control one (scntl1) , bit 7 is asserted and the LSI53C825A is sending data. extcc = 0 if the LSI53C825A is receiving data.) sxferp = 100 ? 25=4 where sxferp synchronous transfer period sscp scsi synchronous core period sscf scsi synchronous core frequency extcc extra clock cycle of data setup operating registers 4-33 table 4.4 and table 4.5 show examples of possible bit combinations. table 4.4 examples of synchronous transfer periods and rates for scsi-1 clk (mhz) scsi clk ? scntl3 bits [6:4] xferp synch. transfer period (ns) synch. send rate (mbytes) synch. receive rate (mbytes) 66.67 3 4 180 5.55 5.55 66.67 3 5 225 4.44 5.55 50 2 4 160 6.25 6.25 50 2 5 200 5 6.25 40 2 4 200 5 5 37.50 1.5 4 160 6.25 6.25 33.33 1.5 4 180 5.55 5.55 25 1 4 160 6.25 6.25 20 1 4 200 5 5 16.67 1 4 240 4.17 4.17 table 4.5 example transfer periods and rates for fast scsi-2 clk (mhz) scsi clk ? scntl3 bits [6:4] xferp synch. transfer period (ns) synch. transfer rate (mbytes) synch. receive transfer rate (mbytes) 66.67 1.5 4 90 11.11 11.11 66.67 1.5 5 112.5 8.88 11.11 50 1 4 80 12.5 12.5 50 1 5 100 10.0 12.5 40 1 4 100 10.0 10.0 37.50 1 4 106.67 9.375 9.375 33.33 1 4 120 8.33 8.33 25 1 4 160 6.25 6.25 20 1 4 200 5 5 16.67 1 4 240 4.17 4.17 4-34 registers mo[4:0] max scsi synchronous offset [4:0] these bits describe the maximum scsi synchronous offset used by the LSI53C825A when transferring synchronous scsi data in either the initiator or target mode. table 4.6 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C825A. these bits determine the LSI53C825A method of transfer for data in and data out phases only; all other information transfers occur asynchronously. table 4.6 maximum synchronous offset mo4 mo3 mo2 mo1 mo0 synchronous offset 0 0 0 0 0 0-asynchronous 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 1 x x x 1 reserved 1 x x 1 x reserved 1 x 1 x x reserved 1 1 x x x reserved operating registers 4-35 register: 0x06 (0x86) scsi destination id (sdid) read/write r reserved [7:4] enc[3:0] encoded destination scsi id [3:0] writing these bits sets the scsi id of the intended initiator or target during scsi reselection or selection phases, respectively. when executing scripts, the scripts processor writes the destination scsi id to this register. the scsi id is de?ned by the user in a scripts select or reselect instruction. the value written is the binary-encoded id. the priority of the 16 possible ids, in descending order, is: register: 0x07 (0x87) general purpose (gpreg) read/write r reserved [7:5] gpio[4:0] general purpose i/o [4:0] these bits are programmed through the general purpose pin control (gpcntl) register as inputs, outputs, or to perform special functions. as an output, these pins can be used to enable or disable external terminators. it is also possible to program these signals as live inputs and sense them through a scripts register to register move 7430 r enc[3:0] x x x x0000 highest lowest 765432101514131211098 754 0 r gpio[4:0] x x x0xxxx 4-36 registers instruction. gpio[3:0] default as inputs and gpio4 defaults as an output pin. when con?gured as inputs, an internal pull-down is enabled. gpio4 can be used to enable or disable v pp , the 12 v power supply to the external ?ash memory. this bit powers up with the power to the external memory disabled. the gpio[1:0] signals can also be controlled from pci con?guration register 0x35. they may be read, but not controlled, from this register. lsi logic software uses gpio3 to detect a differential board. if the pin is pulled low externally, the board will be con?gured by sdms software as a differential board. if it is pulled high or left ?oating, sdms software will con?gure it as an se board. the lsi logic pci to scsi host adapters use the gpio4 pin in the process of ?ashing a new sdms software rom. lsi logic software uses the gpio0 pin to toggle scsi device leds, turning on the led whenever the LSI53C825A is on the scsi bus. sdms software drives this pin low to turn on the led, or drives it high to turn off the led. sdms software uses the gpio[1:0] pins to support serial eeprom access. when serial eeprom access is enabled, gpio1 is used as a clock and gpio0 is used as data. the pins are controlled from pci con?guration register 0x35. they may be read, but not controlled, from this register. operating registers 4-37 register: 0x08 (0x88) scsi first byte received (sfbr) read/write ib scsi first byte received [7:0] this register contains the ?rst byte received in any asynchronous information transfer phase. for example, when a LSI53C825A is operating in the initiator mode, this register contains the ?rst byte received in the message-in, status, and data-in phases. when a block move instruction is executed for a particular phase, the ?rst byte received is stored in this registereven if the present phase is the same as the last phase. the ?rst byte received value for a particular input phase is not valid until after a move instruction is executed. this register is also the accumulator for register read-modify-writes with the scsi first byte received (sfbr) as the destination. this allows bit testing after an operation. the scsi first byte received (sfbr) is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with a byte stored in system memory, the byte must ?rst be moved to an intermediate LSI53C825A register (such as the scratch register), and then to the sfbr. this register also contains the state of the lower eight bits of the scsi data bus during the selection phase if the com bit in the dma control (dcntl) register is clear. 7 0 ib 00000000 4-38 registers register: 0x09 (0x89) scsi output control latch (socl) read/write req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 msg assert scsi msg/ signal 2 c/d assert scsi c_d/ signal 1 i/o assert scsi i_o/ signal 0 this register is used primarily for diagnostic testing or programmed i/o operation. it is controlled by the scripts processor when executing scsi scripts. scsi output control latch (socl) is used only when transferring data using programmed i/o. some bits are set or cleared when executing scsi scripts. do not write to the register once the LSI53C825A starts executing normal scsi scripts. 76543210 req ack bsy sel atn msg c/d i/o 00000000 operating registers 4-39 register: 0x0a (0x09) scsi selector id (ssid) read only val scsi valid 7 if val is asserted, then the two scsi ids are detected on the bus during a bus-initiated selection or reselection, and the encoded destination scsi id bits below are valid. if val is deasserted, only one id is present and the contents of the encoded destination id are meaningless. r reserved [6:4] enid[3:0] encoded destination scsi id [3:0] reading the scsi destination id (sdid) register immediately after the LSI53C825A is selected or reselected returns the binary-encoded scsi id of the device that performed the operation. these bits are invalid for targets that are selected under the single initiator option of the scsi-1 speci?cation. this condition is detected by examining the val bit above. register: 0x0b (0x8b) scsi bus control lines (sbcl) read only req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 76 43 0 val r enid[3:0] 0 x x x0000 76543210 req ack bsy sel atn msg c/d i/o xxxxxxxx 4-40 registers msg assert scsi msg/ signal 2 c/d assert scsi c_d/ signal 1 i/o assert scsi i_o/ signal 0 this register returns the scsi control line status. a bit is set when the corresponding scsi control line is asserted. these bits are not latched; they are a true representation of what is on the scsi bus at the time the register is read. the resulting read data is synchronized before being presented to the pci bus to prevent parity errors from being passed to the system. this register is used for diagnostics testing or operation in the low level mode. register: 0x0c (0x8c) dma status (dstat) read only reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C825A stack interrupts). the dip bit in the interrupt status (istat) register is also cleared. it is possible to mask dma interrupt conditions individually through the dma interrupt enable (dien) register. when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0), and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure that the interrupts clear properly. see chapter 2, functional description, for more information on interrupts. dfe dma fifo empty 7 this status bit is set when the dma fifo is empty. it is possible to use it to determine if any data resides in the fifo when an error occurs and an interrupt is generated. this bit is a pure status bit and does not cause an interrupt. 76543210 dfe mdpe bf abrt ssi sir r iid 100000 x0 operating registers 4-41 mdpe master data parity error 6 this bit is set when the LSI53C825A as a master detects a data parity error, or a target device signals a parity error during a data phase. this bit is completely disabled by the master parity error enable bit (bit 3 of chip test four (ctest4) ). bf bus fault 5 this bit is set when a pci bus fault condition is detected. a pci bus fault can only occur when the LSI53C825A is bus master, and is de?ned as a cycle that ends with a bad address or target abort condition. abrt aborted 4 this bit is set when an abort condition occurs. an abort condition occurs when a software abort command is issued by setting bit 7 of the interrupt status (istat) register. ssi single step interrupt 3 if the single step mode bit in the dma control (dcntl) register is set, this bit is set and an interrupt generated after successful execution of each scripts instruction. sir scripts interrupt instruction received 2 this status bit is set whenever an interrupt instruction is evaluated as true. r reserved 1 iid illegal instruction detected 0 this status bit is set any time an illegal or reserved instruction opcode is detected, whether the LSI53C825A is operating in single step mode or automatically executing scsi scripts. any of the following conditions during instruction execution also sets this bit: the LSI53C825A is executing a wait disconnect instruction and the scsi req line is asserted without a disconnect occurring. a block move instruction is executed with 0x000000 loaded into the dma byte counter (dbc) register, indicating there are zero bytes to move. 4-42 registers during a transfer control instruction, the compare data (bit 18) and compare phase (bit 17) bits are set in the dma byte counter (dbc) register while the LSI53C825A is in target mode. during a transfer control instruction, the carry test bit (bit 21) is set and either the compare data (bit 18) or compare phase (bit 17) bit is set. a transfer control instruction is executed with the reserved bit 22 set. a transfer control instruction is executed with the wait for valid phase bit (bit 16) set while the chip is in target mode. a load and store instruction is issued with the memory address mapped to the operating registers of the chip, not including rom or ram. a load and store instruction is issued when the register address is not aligned with the memory address. a load and store instruction is issued with bit 5 in the dma command (dcmd) register cleared or bits 3 or 2 set. a load and store instruction when the count value in the dma byte counter (dbc) register is not set at 1to4. a load and store instruction attempts to cross a dword boundary. a memory move instruction is executed with one of the reserved bits in the dma command (dcmd) register set. a memory move instruction is executed with the source and destination addresses not aligned. operating registers 4-43 register: 0x0d (0x8d) scsi status zero (sstat0) read only ilf sidl least signi?cant byte full 7 this bit is set when the least signi?cant byte in the scsi input data latch (sidl) register contains data. data is transferred from the scsi bus to the scsi input data latch (sidl) register before being sent to the dma fifo and then to the host bus. the scsi input data latch (sidl) register contains scsi data received asynchronously. synchronous data received does not ?ow through this register. orf sodr least signi?cant byte full 6 this bit is set when the least signi?cant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the sodr is used by the scsi logic as a second storage register when sending data synchronously. it is not readable or writable by the user. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. olf sodl least signi?cant byte full 5 this bit is set when the least signi?cant byte in the scsi output data latch (sodl) contains data. the scsi out- put data latch (sodl) register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the scsi output data latch (sodl) register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bustothe scsi output data latch (sodl) register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. 76543210 ilf orf olf aip loa woa rst/ sdp0/ 00000000 4-44 registers aip arbitration in progress 4 arbitration in progress (aip = 1) indicates that the LSI53C825A has detected a bus free condition, asserted bsy, and asserted its scsi id onto the scsi bus. loa lost arbitration 3 when set, loa indicates that the LSI53C825A has detected a bus free condition, arbitrated for the scsi bus, and lost arbitration due to another scsi device asserting the sel/ signal. woa won arbitration 2 when set, woa indicates that the LSI53C825A has detected a bus free condition, arbitrated for the scsi bus and won arbitration. the arbitration mode selected in the scsi control zero (scntl0) register must be full arbitration and selection to set this bit. rst/ scsi rst/ signal 1 this bit reports the current status of the scsi rst/ signal, and the rst signal (bit 6) in the interrupt status (istat) register. this bit is not latched and may change as it is read. sdp0/ scsi sdp0/ parity signal 0 this bit represents the present state of the scsi sdp0/ parity signal. this signal is not latched and may change as it is read. register: 0x0e (0x8e) scsi status one (sstat1) read only ff[3:0] fifo flags [7:4] these four bits, along with scsi status two (sstat2) , bit 4, de?ne the number of bytes or words that currently reside in the LSI53C825A scsi synchronous data fifo. these bits are not latched and they will change as data moves through the fifo. 7 43210 ff[3:0] sdpol msg c/d i/o 0000 xxxx operating registers 4-45 sdp0l latched scsi parity 3 this bit re?ects the scsi parity signal (sdp0/), corresponding to the data latched in the scsi input data latch (sidl) . it changes when a new byte is latched into the least signi?cant byte of the scsi input data latch (sidl) register. this bit is active high, in other words, it is set when the parity signal is active. msg scsi msg/ signal 2 c/d scsi c_d/ signal 1 i/o scsi i_o/ signal 0 these scsi phase status bits are latched on the asserting edge of sreq/ when operating in either the ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo 000000 000011 000102 000113 001004 001015 001106 001117 010008 010019 0101010 0101111 0110012 0110113 0111014 0111115 1000016 4-46 registers initiator or target mode. these bits are set when the corresponding signal is active. they are useful when operating in the low level mode. register: 0x0f (0x8f) scsi status two (sstat2) read only ilf1 sidl most signi?cant byte full 7 this bit is set when the most signi?cant byte in the scsi input data latch (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch (sidl) register before being sent to the dma fifo and then to the host bus. the scsi input data latch (sidl) register contains scsi data received asynchronously. synchronous data received does not ?ow through this register. orf1 sodr most signi?cant byte full 6 this bit is set when the most signi?cant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it is not accessible to the user. this bit is used to determine how many bytes reside in the chip when an error occurs. olf1 sodl most signi?cant byte full 5 this bit is set when the most signi?cant byte in the scsi output data latch (sodl) contains data. the scsi out- put data latch (sodl) register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the scsi output data latch (sodl) register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bustothe scsi output data latch (sodl) register, and then to the scsi bus. the sodr buffer register is not 76543210 ilf orf1 olf1 ff4 spl1 diff ldsc sdp1 00000000 operating registers 4-47 used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. ff4 fifo flags, bit 4 4 this is the most signi?cant bit in the scsi fifo flags ?eld, with the rest of the bits in scsi status one (sstat1) . for a complete description of this ?eld, see the de?nition for scsi status one (sstat1) , bits [7:4]. spl1 latched scsi parity for sd[15:8] 3 this active high bit re?ects the scsi odd parity signal corresponding to the data latched into the most signi?cant byte in the scsi input data latch (sidl) register. diff diffsens mismatch 2 if this bit is reset, the correct cable type has been connected for the differential operation. if this bit is set, a se cable has been connected to the devices diffsens pin. ldsc last disconnect 1 this bit is used in conjunction with the connected (con) bit in scsi control one (scntl1) . it allows the user to detect the case in which a target device disconnects, and then some scsi device selects or reselects the LSI53C825A. if the connected bit is asserted and the ldsc bit is asserted, a disconnect is indicated. this bit is set when the connected bit in scsi control one (scntl1) is off. this bit is cleared when a block move instruction is executed while the connected bit in scsi control one (scntl1) is on. sdp1 scsi sdp1 parity signal 0 this bit represents the present state of the scsi sdp1/ parity signal. it is unlatched and may change as it is read. 4-48 registers registers: 0x10C0x13 (0x90C0x93) data structure address (dsa) read/write dsa data structure address [31:0] this 32-bit register contains the base address used for all table indirect calculations. the data structure address (dsa) register is usually loaded prior to starting an i/o, but it is possible for a scripts memory move to load the dsa during the i/o. during any memory-to-memory move operation, the contents of this register is preserved. the power-up value of this register is indeterminate. register: 0x14 (0x94) interrupt status (istat) read/write this is the only register that is accessible by the host cpu while a LSI53C825A is executing scripts (without interfering in the operation of the function). it is used to poll for interrupts if hardware interrupts are disabled. read this register after servicing an interrupt to check for stacked interrupts. for more information on interrupt handling refer to chapter 2, functional description. abrt abort operation 7 setting this bit aborts the current operation under execution by the LSI53C825A. if this bit is set and an interrupt is received, clear this bit before reading the dma status (dstat) register to prevent further aborted interrupts from being generated. the sequence to abort any operation is: 1. set this bit. 31 0 dsa[31:0] 00000000000000000000000000000000 76543210 abrt srst sigp sem con intf sip dip 00000000 operating registers 4-49 2. wait for an interrupt. 3. read the interrupt status (istat) register. 4. if the scsi interrupt pending bit is set, then read the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) register to determine the cause of the scsi interrupt and go back to step 2. 5. if the scsi interrupt pending bit is clear, and the dma interrupt pending bit is set, then write 0x00 value to this register. 6. read the dma status (dstat) register to verify the aborted interrupt and to see if any other interrupting conditions have occurred. srst software reset 6 setting this bit resets the LSI53C825A. all operating registers are cleared to their respective default values and all scsi signals are deasserted. setting this bit does not assert the scsi rst/ signal. this reset does not clear the id mode bit or any of the pci con?guration registers. this bit is not self-clearing; it must be cleared to clear the reset condition (a hardware reset also clears this bit). sigp signal process 5 sigp is a r/w bit that is writable at any time, and polled and reset using chip test two (ctest2) . the sigp bit is used in various ways to pass a ?ag to or from a running scripts instruction. the only scripts instruction directly affected by the sigp bit is wait for selection/reselection. setting this bit causes that instruction to jump to the alternate address immediately. the instructions at the alternate jump address should check the status of sigp to determine the cause of the jump. the sigp bit is usable at any time and is not restricted to the wait for selection/reselection condition. sem semaphore 4 the scripts processor may set this bit using a scripts register write instruction. an external processor may also set it while the LSI53C825A is executing a scripts operation. this bit enables the LSI53C825A to 4-50 registers notify an external processor of a prede?ned condition while scripts are running. the external processor may also notify the LSI53C825A of a prede?ned condition and the scripts processor may take action while scripts are executing. con connected 3 this bit is automatically set any time the LSI53C825A is connected to the scsi bus as an initiator or as a target. it is set after successfully completing selection or when the LSI53C825A responds to a bus-initiated selection or reselection. it is also set after the scsi function wins arbitration when operating in low level mode. when this bit is cleared, the LSI53C825A is not connected to the scsi bus. intf interrupt-on-the-fly 2 this bit is asserted by an intfly instruction during scripts execution. scripts programs do not halt when the interrupt occurs. this bit can be used to notify a service routine, running on the main processor while the scripts processor is still executing a scripts program. if this bit is set, when the interrupt status (istat) register is read it is not automatically cleared. to clear this bit, write it to a one. the reset operation is self-clearing. note: if the intf bit is set but sip or dip is not set, do not attempt to read the other chip status registers. an interrupt-on-the-?y must be cleared before servicing any other interrupts indicated by sip or dip. this bit must be written to one in order to clear it after it has been set. sip scsi interrupt pending 1 this status bit is set when an interrupt condition is detected in the scsi portion of the LSI53C825A. the following conditions cause a scsi interrupt to occur: a phase mismatch (initiator mode) or satn/ becomes active (target mode) an arbitration sequence completes a selection or reselection time-out occurs operating registers 4-51 the LSI53C825A is selected the LSI53C825A is reselected a scsi gross error occurs an unexpected disconnect occurs a scsi reset occurs a parity error is detected the handshake-to-handshake timer is expired the general purpose timer is expired to determine exactly which condition(s) caused the interrupt, read the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers. dip dma interrupt pending 0 this status bit is set when an interrupt condition is detected in the dma portion of the LSI53C825A. the following conditions cause a dma interrupt to occur: a pci parity error is detected a bus fault is detected an abort condition is detected a scripts instruction is executed in single step mode a scripts interrupt instruction is executed an illegal instruction is detected to determine exactly which condition(s) caused the interrupt, read the dma status (dstat) register. 4-52 registers register: 0x18 (0x98) chip test zero (ctest0) read/write fmt byte empty in dma fifo [7:0] this was a general purpose read/write register in previous lsi53c8xx family chips. although it is still a read/write register, lsi logic reserves the right to use these bits for future lsi53c8xx family enhancements. register: 0x19 (0x99) chip test one (ctest1) read only fmt[3:0] byte empty in dma fifo [7:4] these bits identify the bottom bytes in the dma fifo that are empty. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is empty, then fmt3 is set. since the fmt ?ags indicate the status of bytes at the bottom of the fifo, if all fmt bits are set, the dma fifo is empty. ffl[3:0] byte full in dma fifo [3:0] these status bits identify the top bytes in the dma fifo that are full. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is full then ffl3 is set. since the ffl ?ags indicate the status of bytes at the top of the fifo, if all ffl bits are set, the dma fifo is full. 7 0 fmt 11111111 7 0 fmt[3:0] ffl[3:0] 11110000 operating registers 4-53 register: 0x1a (0x9a) chip test two (ctest2) read/write ddir data transfer direction 7 this status bit indicates which direction data is being transferred. when this bit is set, the data is transferred from the scsi bus to the host bus. when this bit is clear, the data is transferred from the host bus to the scsi bus. sigp signal process 6 this bit is a copy of the sigp bit in the interrupt status (istat) register (bit 5). the sigp bit is used to signal a running scripts instruction. when this register is read, the sigp bit in the istat0 register is cleared. cio con?gured as i/o 5 this bit is de?ned as the con?guration i/o enable status bit. this read only bit indicates if the chip is currently enabled as i/o space. note: bits 4 and 5 may be set if the chip is dual-mapped. cm con?gured as memory 4 this bit is de?ned as the con?guration memory enable status bit. this read only bit indicates if the chip is currently enabled as memory space. note: bits 4 and 5 may be set if the chip is dual-mapped. srtch scratcha/b operation 3 this bit controls the operation of the scratch register a (scratcha) and scratch register b (scratchb) registers. when it is set, scratchb contains the ram base address value from the pci con?guration ram base address register. this is the base address for the 4 kbyte internal ram. in addition, the scratch register a (scratcha) register displays the memory-mapped based address of the chip operating registers. when this 76543210 ddir sigp cio cm srtch teop dreq dack 00xx0001 4-54 registers bit is clear, the scratch register a (scratcha) and scratch register b (scratchb) registers return to normal operation. note: bit 3 is the only writable bit in this register. all other bits are read only. when modifying this register, all other bits must be written to zero. do not execute a read-modify-write to this register. teop scsi true end of process 2 this bit indicates the status of the LSI53C825A internal teop signal. the teop signal acknowledges the completion of a transfer through the scsi portion of the LSI53C825A. when this bit is set, teop is active. when this bit is cleared, teop is inactive. dreq data request status 1 this bit indicates the status of the LSI53C825A internal data request signal (dreq). when this bit is set, dreq is active. when this bit is cleared, dreq is inactive. dack data acknowledge status 0 this bit indicates the status of the LSI53C825A internal data acknowledge signal (dack/). when this bit is set, dack/ is inactive. when this bit is cleared, dack/ is active. register: 0x1b (0x9b) chip test three (ctest3) read/write v[3:0] chip revision level [7:4] these bits identify the chip revision level for software purposes. it should have the same value as the lower nibble of the pci revision id register, at address 0x08 in the con?guration space. flf flush dma fifo 3 when this bit is set, data residing in the dma fifo is transferred to memory, starting at the address in the dma 7 43210 v[3:0] flf clf fm wrie xxxx 0000 operating registers 4-55 next address (dnad) register. the internal dmawr signal, controlled by the chip test five (ctest5) register, determines the direction of the transfer. this bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C825A. note: polling of fifo ?ags is allowed during ?ush operations. clf clear dma fifo 2 when this bit is set, all data pointers for the dma fifo are cleared. any data in the fifo is lost. after the LSI53C825A successfully clears the appropriate fifo pointers and registers, this bit automatically clears. note: this bit does not clear the data visible at the bottom of the fifo. fm fetch pin mode 1 when set, this bit causes the fetch/ pin to deassert during indirect and table indirect read operations. fetch/ is only active during the opcode portion of an instruction fetch. this allows the storage of scripts in a prom while data tables are stored in ram. if this bit is not set, fetch/ is asserted for all bus cycles during instruction fetches. wrie write and invalidate enable 0 this bit, when set, causes the issuing of write and invalidate commands on the pci bus whenever legal. the write and invalidate enable bit in the pci con?guration command register must also be set in order for the chip to generate write and invalidate commands. 4-56 registers registers: 0x1cC0x1f (0x9cC0x9f) temporary (temp) read/write temp temporary [31:0] this 32-bit register stores the return instruction address pointer from the call instruction. the address pointer stored in this register is loaded into the dma scripts pointer (dsp) register when a return instruction is executed. this address points to the next instruction to execute. do not write to this register while the LSI53C825A is executing scripts. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. register: 0x20 (0xa0) dma fifo (dfifo) read/write bo byte offset counter [7:0] these bits, along with bits [1:0] in the chip test five (ctest5) register, indicate the amount of data transferred between the scsi core and the dma core. it is used to determine the number of bytes in the dma fifo when an interrupt occurs. these bits are unstable while data is being transferred between the two cores. once the chip has stopped transferring data, these bits are stable. the dma fifo (dfifo) register counts the number of bytes transferred between the dma core and the scsi core. the dma byte counter (dbc) register counts the number of bytes transferred across the host bus. the 31 0 temp xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 7 0 bo x0000000 operating registers 4-57 difference between these two counters represents the number of bytes remaining in the dma fifo. the following steps determine how many bytes are left in the dma fifo when an error occurs, regardless of the transfer direction: step 1. if the dma fifo size is set to 88 bytes, subtract the seven least signi?cant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. if the dma fifo size is set to 536 bytes (using bit 5 of the chip test five (ctest5) register), subtract the 10 least signi?cant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo (dfifo) register. step 2. if the dma fifo size is set to 88 bytes, and the result with 0x7f for a byte count between zero and 64. if the dma fifo size is set to 536 bytes, and the result with 0x3ff for a byte count between zero and 536. note: if trying to calculate the total number of bytes in both the dma fifo and scsi logic, see section 2.4.8.1, data paths, in chapter 2, functional description. register: 0x21 (0xa1) chip test four (ctest4) read/write bdis burst disable 7 when set, this bit causes the LSI53C825A to perform back to back cycles for all transfers. when this bit is cleared, back to back transfers for opcode fetches and burst transfers for data moves are performed. 765432 0 bdis zmod zsd srtm mpee fbl[2:0] 00000000 4-58 registers zmod high impedance mode 6 setting this bit causes the LSI53C825A to place all output and bidirectional pins into a high impedance state. in order to read data out of the LSI53C825A, this bit must be cleared. this bit is intended for board level testing only. do not set this bit during normal system operation. zsd scsi data high impedance 5 setting this bit causes the LSI53C825A to place the scsi data bus sd[15:0] and the parity lines sdp[1:0] in a high impedance state. in order to transfer data on the scsi bus, clear this bit. srtm shadow register test mode 4 setting this bit allows access to the shadow registers used by memory-to-memory move operations. when this bit is set, register accesses to the temporary (temp) and data structure address (dsa) registers are directed to the shadow copies stemp (shadow temp) and sdsa (shadow dsa). the registers are shadowed to prevent them from being overwritten during a memory-to-memory move operation. the data structure address (dsa) and temporary (temp) registers contain the base address used for table indirect calculations, and the address pointer for a call or return instruction, respectively. this bit is intended for manufacturing diagnostics only and should not be set during normal operations. mpee master parity error enable 3 setting this bit enables parity checking during master data phases. a parity error during a bus master read is detected by the LSI53C825A. a parity error during a bus master write is detected by the target, and the LSI53C825A is informed of the error by the perr/ pin being asserted by the target. when this bit is cleared, the LSI53C825A does not interrupt if a master parity error occurs. this bit is cleared at power-up. operating registers 4-59 fbl[2:0] fifo byte control [2:0] these bits steer the contents of the chip test six (ctest6) register to the appropriate byte lane of the 64-bit dma fifo. if the fbl3 bit is set, then fbl2 through fbl0 determine which of eight byte lanes can be read or written. when cleared, the byte lane read or written is determined by the current contents of the dma next address (dnad) and dma byte counter (dbc) registers. each of the eight bytes that make up the 64-bit dma fifo is accessed by writing these bits to the proper value. for normal operation, fbl3 must equal zero. register: 0x22 (0xa2) chip test five (ctest5) read/write adck clock address incrementor 7 setting this bit increments the address pointer contained in the dma next address (dnad) register. the dma next address (dnad) register is incremented based on the dnad contents and the current dma byte counter (dbc) value. this bit automatically clears itself after incrementing the dma next address (dnad) register. bbck clock byte counter 6 setting this bit decrements the byte count contained in the 24-bit dma byte counter (dbc) register. it is decremented based on the dbc contents and the current dma next address (dnad) value. this bit automatically fbl3 fbl2 fbl1 fbl0 dma fifo byte lane pins 0 x x x disabled n/a 1 0 0 0 0 d[7:0] 1 0 0 1 1 d[15:8] 1 0 1 0 2 d[23:16] 1 0 1 1 3 d[31:24] 76543210 adck bbck dfs masr ddir bl2 bo[9:8] 00000xxx 4-60 registers clears itself after decrementing the dma byte counter (dbc) register. dfs dma fifo size 5 this bit controls the size of the dma fifo. when clear, the dma fifo appears as only 88 bytes deep. when set, the dma fifo size increases to 536 bytes. using an 88-byte fifo allows software written for other lsi53c8xx family chips to properly calculate the number of bytes residing in the chip after a target disconnect. the default value of this bit is zero. masr master control for set or reset pulses 4 this bit controls the operation of bit 3. when this bit is set, bit 3 asserts the corresponding signals. when this bit is cleared, bit 3 deasserts the corresponding signals. do not change this bit and bit 3 in the same write cycle. ddir dma direction 3 setting this bit either asserts or deasserts the internal dma write (dmawr) direction signal depending on the current status of the masr bit in this register. asserting the dmawr signal indicates that data is transferred from the scsi bus to the host bus. deasserting the dmawr signal transfers data from the host bus to the scsi bus. bl2 burst length bit 2 2 this bit works with bits 6 and 7 (bl[1:0]) in the dma mode (dmode) , 0x38 (0xb8) register to determine the burst length. for complete de?nitions of this ?eld, refer to the descriptions of dma mode (dmode) , bits 6 and 7. this bit is disabled if an 88-byte fifo is selected by clearing the dma fifo size bit. bo[9:8] dma fifo byte offset counter, bits [9:8] [1:0] these are the upper two bits of the dfboc. the dfboc consists of these bits and the dma fifo (dfifo), bits [7:0]. operating registers 4-61 register: 0x23 (0xa3) chip test six (ctest6) read/write df dma fifo [7:0] writing to this register writes data to the appropriate byte lane of the dma fifo as determined by the fbl bits in the chip test four (ctest4) register. reading this register unloads data from the appropriate byte lane of the dma fifo as determined by the fbl bits in the chip test four (ctest4) register. data written to the fifo is loaded into the top of the fifo. data read out of the fifo is taken from the bottom. to prevent dma data from being corrupted, this register should not be accessed before starting or restarting scripts operation. write to this register only when testing the dma fifo using the chip test four (ctest4) register. writing to this register while the test mode is not enabled produces unexpected results. 7 0 df 00000000 4-62 registers register: 0x24C0x26 (0xa4C0xa6) dma byte counter (dbc) read/write dbc dma byte counter [23:0] this 24-bit register determines the number of bytes transferred in a block move instruction. while sending data to the scsi bus, the counter is decremented as data is moved into the dma fifo from memory. while receiving data from the scsi bus, the counter is decremented as data is written to memory from the LSI53C825A. the dbc counter is decremented each time data is transferred on the pci bus. it is decremented by an amount equal to the number of bytes that are transferred. the maximum number of bytes that can be transferred in any one block move command is 16,777,215 bytes. the maximum value that can be loaded into the dma byte counter (dbc) register is 0xffffff. if the instruction is a block move and a value of 0x000000 is loaded into the dma byte counter (dbc) register, an illegal instruction interrupt occurs if the LSI53C825A is not in the target mode, command phase. the dma byte counter (dbc) register is also used to hold the least signi?cant 24 bits of the ?rst dword of a scripts fetch, and to hold the offset value during table indirect i/o scripts. the power-up value of this register is indeterminate. 23 0 dbc xxxxxxxxxxxxxxxxxxxxxxxx operating registers 4-63 register: 0x27 (0xa7) dma command (dcmd) read/write dcmd dma command [7:0] this 8-bit register determines the instruction for the LSI53C825A to execute. this register has a different format for each instruction. for a complete description see chapter 5, scsi scripts instruction set. register: 0x28C0x2b (0xa8C0xab) dma next address (dnad) read/write dnad dma next address [31:0] this 32-bit register contains the general purpose address pointer. at the start of some scripts operations, its value is copied from the dma scripts pointer save (dsps) register. its value may not be valid except in certain abort conditions. the default value of this register is zero. this register should not be used to determine data addresses during a phase mismatch interrupt, as its value is not always correct for this use. the dma byte counter (dbc) , dma fifo (dfifo) , and dma scripts pointer save (dsps) registers should be used to calculate residual byte counts and addresses as described in the data paths section in chapter 2, func- tional description. 7 0 dcmd xxxxxxxx 31 0 dnad 00000000000000000000000000000000 4-64 registers registers: 0x2cC0x2f (0xacC0xaf) dma scripts pointer (dsp) read/write dsp dma scripts pointer [31:0] to execute scsi scripts, the address of the ?rst scripts instruction must be written to this register. in normal scripts operation, once the starting address of the script is written to this register, scripts are automatically fetched and executed until an interrupt condition occurs. in the single step mode, there is a single step interrupt after each instruction is executed. the dma scripts pointer (dsp) register does not need to be written with the next address, but the start dma bit (bit 2, dma con- trol (dcntl) register) must be set each time the step interrupt occurs to fetch and execute the next scripts command. when writing this register eight bits at a time, writing the upper eight bits begins execution of scsi scripts. the default value of this register is zero. registers: 0x30C0x33 (0xb0C0xb3) dma scripts pointer save (dsps) read/write dsps dma scripts pointer save [31:0] this register contains the second dword of a scripts instruction. it is overwritten each time a scripts instruction is fetched. when a scripts interrupt instruction is executed, this register holds the interrupt vector. the power-up value of this register is indeterminate. 31 0 dsp 00000000000000000000000000000000 31 0 dsps xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx operating registers 4-65 registers: 0x34C0x37 (0xb4C0xb7) scratch register a (scratcha) read/write scratcha scratch register a [31:0] this is a general purpose, user-de?nable scratch pad register. apart from cpu access, only register read/write and memory moves into the scratch register alter its contents. the LSI53C825A cannot fetch scripts instructions from this location. when bit 3 in the chip test two (ctest2) register is set, this register contains the memory mapped base address of the operating registers. setting chip test two (ctest2) , bit 3 only causes the base address to appear in this register; any information that was previously in the register will remain intact. any writes to this register while chip test two (ctest2) , bit 3 is set will pass through to the actual scratch register a (scratcha) register. the power-up value of this register is indeterminate. register: 0x38 (0xb8) dma mode (dmode) read/write bl[1:0] burst length [7:6] these bits control the maximum number of dwords transferred per bus ownership, regardless of whether the transfers are back-to-back, burst, or a combination of both. this value is also independent of the width (64 or 32 bits) of the data transfer on the pci bus. the LSI53C825A asserts the bus request (req/) output when the dma fifo can accommodate a transfer of at least one burst threshold of data. bus request (req/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even if less than a full burst of 31 0 scratcha xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 76543210 bl[1:0] siom diom er ermp bof man 00000000 4-66 registers transfers is performed. the LSI53C825A inserts a fairness delay of four clks between burst transfers (as set in bl[1:0]) during normal operation. the fairness delay is not inserted during pci retry cycles. this gives the cpu and other bus master devices the opportunity to access the pci bus between bursts. siom source i/o-memory enable 5 this bit is de?ned as an i/o memory enable bit for the source address of a memory move or block move command. if this bit is set, then the source address is in i/o space; and if cleared, then the source address is in memory space. this function is useful for register-to-memory operations using the memory move instruction when a LSI53C825A is i/o mapped. bits 4 and 5 of the chip test two (ctest2) register are used to determine the con?guration status of the LSI53C825A. diom destination i/o-memory enable 4 this bit is de?ned as an i/o memory enable bit for the destination address of a memory move or block move command. if this bit is set, then the destination address is in i/o space; and if cleared, then the destination address is in memory space. this function is useful for memory-to-register operations using the memory move instruction when a LSI53C825A is i/o mapped. bits 4 and 5 of the chip test two (ctest2) register are used to determine the con?guration status of the LSI53C825A. bl2 (ctest5 bit 2) bl1 bl0 burst length 0 0 0 2-transfer burst 0 0 1 4-transfer burst 0 1 0 8-transfer burst 0 1 1 16-transfer burst 1 0 0 32-transfer burst 1 1 0 1 64-transfer burst 1 1 1 0 128-transfer burst 1 1 1 1 reserved 1. only valid if the fifo size is set to 536 bytes. operating registers 4-67 erl enable read line 3 this bit enables a pci read line command. if the pci cache mode is enabled by setting bits in the pci cache line size register, this chip issues a read line command on all read cycles if other conditions are met. for more information on these conditions, refer to chapter 3, sig- nal descriptions. ermp enable read multiple 2 this bit, when set, causes read multiple commands to be issued on the pci bus after certain conditions have been met. these conditions are described in chapter 3, signal descriptions. bof burst opcode fetch enable 1 setting this bit causes the LSI53C825A to fetch instructions in burst mode. speci?cally, the chip bursts in the ?rst two dwords of all instructions using a single bus ownership. if the instruction is a memory-to-memory move type, the third dword is accessed in a subsequent bus ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move type, the chip accesses the remaining two dwords in a subsequent bus ownership, thereby fetching the four dwords required in two bursts of two dwords each. this bit has no effect if scripts instruction prefetching is enabled. man manual start mode 0 setting this bit prevents the LSI53C825A from automatically fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. when this bit is set, the start dma bit in the dma control (dcntl) register must be set to begin scripts execution. clearing this bit causes the LSI53C825A to automatically begin fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. this bit normally is not used for scsi scripts operations. 4-68 registers register: 0x39 (0xb9) dma interrupt enable (dien) read/write r reserved 7 mdpe master data parity error 6 bf bus fault 5 abrt aborted 4 ssi single step interrupt 3 sir scripts interrupt instruction received 2 r reserved 1 iid illegal instruction detected 0 this register contains the interrupt mask bits corresponding to the interrupting conditions described in the dma status (dstat) register. an interrupt is masked by clearing the appropriate mask bit. masking an interrupt prevents irq from being asserted for the corresponding interrupt, but the status bit is still set in the dma status (dstat) register. masking an interrupt does not prevent setting the interrupt status (istat) dip. all dma interrupts are considered fatal, therefore scripts stops running when this condition occurs, whether or not the interrupt is masked. setting a mask bit enables the assertion of irq for the corresponding interrupt. (a masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through; interrupt stacking begins when either the interrupt status (istat) sip or dip bit is set.) the LSI53C825A irq/ output is latched; once asserted, it remains asserted until the interrupt is cleared by reading the appropriate status register. masking an interrupt after the irq/ output is asserted does not cause irq/ to be deasserted. for more information on interrupts, see chapter 2, functional description. 76543210 r mdpe bf abrt ssi sir r iid x00000 x0 operating registers 4-69 register: 0x3a (0xba) scratch byte register (sbr) read/write sbr scratch byte register [7:0] this is a general purpose register. apart from cpu access, only register read/write and memory moves into this register alter its contents. the default value of this register is zero. this register is called the dma watchdog timer on previous lsi53c8xx family products. register: 0x3b (0xbb) dma control (dcntl) read/write clse cache line size enable 7 setting this bit enables the LSI53C825A to sense and react to cache line boundaries set up by the dma mode (dmode) or pci cache line size register, whichever contains the smaller value. clearing this bit disables the cache line size logic and the LSI53C825A monitors the cache line size using the dma mode (dmode) register. pff prefetch flush 6 setting this bit causes the prefetch unit to ?ush its contents. this bit clears after the ?ush is complete. pfen prefetch enable 5 setting this bit enables the prefetch unit if the burst size is equal to or greater than four. for more information on scripts instruction prefetching, see chapter 2, func- tional description. 7 0 sbr 00000000 76543210 clse pff pfen ssm irqm std irqd com 00000000 4-70 registers ssm single step mode 4 setting this bit causes the LSI53C825A to stop after executing each scripts instruction, and generate a single step interrupt. when this bit is cleared the LSI53C825A does not stop after each instruction. it continues fetching and executing instructions until an interrupt condition occurs. for normal scsi scripts operation, keep this bit cleared. to restart the LSI53C825A after it generates a scripts step interrupt, read the interrupt status (istat) and dma status (dstat) registers to recognize and clear the interrupt. then set the start dma bit in this register. irqm irq mode 3 when set, this bit enables a totem pole driver for the irq pin. when cleared, this bit enables an open drain driver for the irq pin with an internal weak pull-up. the bit should remain cleared to retain full pci compliance. std start dma operation 2 the LSI53C825A fetches a scsi scripts instruction from the address contained in the dma scripts pointer (dsp) register when this bit is set. this bit is required if the LSI53C825A is in one of the following modes: manual start mode C bit 0 in the dma mode (dmode) register is set single step mode C bit 4 in the dma control (dcntl) register is set when the LSI53C825A is executing scripts in manual start mode, the start dma bit must be set to start instruction fetches, but need not be set again until an interrupt occurs. when the LSI53C825A is in single step mode, set the start dma bit to restart execution of scripts after a single step interrupt. irqd irq disable 1 setting this bit disables the irq pin. clearing the bit enables normal operation. as with any other register other than interrupt status (istat) , this register cannot be accessed except by a scripts instruction during scripts execution. for more information on the use of this bit in interrupt handling, see chapter 2, functional description. operating registers 4-71 com lsi53c700 family compatibility 0 when the com bit is cleared, the LSI53C825A behaves in a manner compatible with the lsi53c700 family; selection/reselection ids are stored in both the scsi selector id (ssid) and scsi first byte received (sfbr) registers. when this bit is set, the id is stored only in the scsi destination id (sdid) register, protecting the sfbr from being overwritten if a selection/reselection occurs during a dma register-to-register operation. this bit is not affected by a software reset. registers: 0x3cC0x3f (0xbcC0xbf) adder sum output (adder) read only adder adder sum output [31:0] this register contains the output of the internal adder, and is used primarily for test purposes. the power-up value for this register is indeterminate. register: 0x40 (0xc0) scsi interrupt enable zero (sien0) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status zero (sist0) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts see chapter 2, functional description. 31 0 adder xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 76543210 m/a cmp sel rsl sge udc rst par 00000000 4-72 registers m/a scsi phase mismatch - initiator mode; scsi atn condition - target mode 7 in the initiator mode, this bit is set when the scsi phase asserted by the target and sampled during sreq/ does not match the expected phase in the scsi output control latch (socl) register. this expected phase is automatically written by scsi scripts. in the target mode, this bit is set when the initiator asserts satn/. see the disable halt on parity error or satn/ condition bit in the scsi control one (scntl1) register for more information on when this status is actually raised. cmp function complete 6 indicates full arbitration and selection sequence is completed. sel selected 5 indicates the LSI53C825A is selected by a scsi initiator device. set the enable response to selection bit in the scsi chip id (scid) register for this to occur. rsl reselected 4 indicates the LSI53C825A is reselected by a scsi target device. set the enable response to reselection bit in the scsi chip id (scid) register for this to occur. sge scsi gross error 3 the following conditions are considered scsi gross errors: data under?ow C reading the scsi fifo when no data is present. data over?ow C writing to the scsi fifo while it is full. offset under?ow C receiving a sack/ pulse in the target mode before the corresponding sreq/ is sent. offset over?ow C receiving a sreq/ pulse in the initiator mode, and exceeding the maximum offset (de?ned by the mo[3:0] bits in the scsi transfer (sxfer) register). a phase change in the initiator mode, with an outstanding sreq/sack offset. operating registers 4-73 residual data in scsi fifo C starting a transfer other than synchronous data receive with data left in the scsi synchronous receive fifo. udc unexpected disconnect 2 this condition only occurs in the initiator mode. it happens when the target to which the LSI53C825A is connected disconnects from the scsi bus unexpectedly. see the scsi disconnect unexpected bit in the scsi control two (scntl2) register for more information on expected versus unexpected disconnects. any discon- nect in the low level mode causes this condition. rst scsi reset condition 1 indicates assertion of the srst/ signal by the LSI53C825A or any other scsi device. this condition is edge-triggered, so multiple interrupts cannot occur because of a single srst/ pulse. par scsi parity error 0 indicates detection by the LSI53C825A of a parity error while receiving or sending scsi data. see the disable halt on parity error or satn/ condition bits in the scsi control one (scntl1) register for more information on when this condition is actually raised. register: 0x41 (0xc1) scsi interrupt enable one (sien1) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status one (sist1) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts refer to chapter 2, functional description. 7 3210 r sto gen hth x x x x x000 4-74 registers r reserved [7:3] sto selection or reselection time-out 2 the scsi device which the LSI53C825A is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register bits [3:0] for more information on the time-out timer. gen general purpose timer expired 1 the general purpose timer is expired. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 the handshake-to-handshake timer is expired. the time measured is the scsi request-to-request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to- handshake timer. register: 0x42 (0xc2) scsi interrupt status zero (sist0) read only reading the scsi interrupt status zero (sist0) register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable zero (sien0) register or not. each bit set indicates occurrence of the corresponding condition. reading the sist0 clears the interrupt status. reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C825A stack interrupts). scsi interrupt conditions are individually masked through the scsi interrupt enable zero (sien0) register. 76543210 m/a cmp sel rsl sge udc rst par 00000000 operating registers 4-75 when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0) , and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clock periods between the reads to ensure the interrupts clear properly. also, if reading the registers when both the interrupt status (istat) sip and dip bits may not be set, read the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers before the dma status (dstat) register to avoid missing a scsi interrupt. for more information on interrupts refer to chapter 2, functional description. m/a initiator mode: phase mismatch; target mode: satn/ active 7 in the initiator mode, this bit is set if the scsi phase asserted by the target does not match the instruction. the phase is sampled when sreq/ is asserted by the target. in the target mode, this bit is set when the satn/ signal is asserted by the initiator. cmp function complete 6 this bit is set when an arbitration only or full arbitration sequence is completed. sel selected 5 this bit is set when the LSI53C825A is selected by another scsi device. the enable response to selection bit must be set in the scsi chip id (scid) register (and the response id zero (respid0) and response id one (respid1) registers must hold the chips id) for the LSI53C825A to respond to selection attempts. rsl reselected 4 this bit is set when the LSI53C825A is reselected by another scsi device. the enable response to reselection bit must be set in the scsi chip id (scid) register (and the response id zero (respid0) and response id one (respid1) registers must hold the chips id) for the LSI53C825A to respond to reselection attempts. sge scsi gross error 3 this bit is set when the LSI53C825A encounters a scsi gross error condition. the following conditions can result in a scsi gross error condition: data under?ow C reading the scsi fifo when no data is present. 4-76 registers data over?ow C writing too many bytes to the scsi fifo, or the synchronous offset causes overwriting the scsi fifo. offset under?ow C the LSI53C825A is operating in the target mode and a sack/ pulse is received when the outstanding offset is zero. offset over?ow C the other scsi device sends a sreq/ or sack/ pulse with data which exceeds the maximum synchronous offset de?ned by the scsi transfer (sxfer) register. a phase change occurs with an outstanding synchronous offset when the LSI53C825A is operating as an initiator. residual data in the synchronous data fifo C a transfer other than synchronous data receive is started with data left in the synchronous data fifo. udc unexpected disconnect 2 this bit is set when the LSI53C825A is operating in the initiator mode and the target device unexpectedly disconnects from the scsi bus. this bit is only valid when the LSI53C825A operates in the initiator mode. when the scsi function operates in the low level mode, any disconnect causes an interrupt, even a valid scsi disconnect. this bit is also set if a selection time-out occurs (it may occur before, at the same time, or stacked after the sto interrupt, since this is not considered an expected disconnect). rst scsi rst/ received 1 this bit is set when the LSI53C825A detects an active srst/ signal, whether the reset is generated external to the chip or caused by the assert srst/ bit in the scsi control one (scntl1) register. this scsi reset detection logic is edge-sensitive, so that multiple interrupts are not generated for a single assertion of the srst/ signal. par parity error 0 this bit is set when the LSI53C825A detects a parity error while receiving scsi data. the enable parity checking bit (bit 3 in the scsi control zero (scntl0) operating registers 4-77 register) must be set for this bit to become active. the LSI53C825A always generates parity when sending scsi data. register: 0x43 (0xc3) scsi interrupt status one (sist1) read only reading the scsi interrupt status one (sist1) register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable one (sien1) register or not. each bit that is set indicates an occurrence of the corresponding condition. reading the sist1 clears the interrupt condition. r reserved [7:3] sto selection or reselection time-out 2 the scsi device which the LSI53C825A is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register, bits [3:0], for more information on the time-out timer. gen general purpose timer expired 1 this bit is set when the general purpose timer expires. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 this bit is set when the handshake-to-handshake timer expires. the time measured is the scsi request to request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to-handshake timer. 7 3210 r sto gen hth x x x x x000 4-78 registers register: 0x44 (0xc4) scsi longitudinal parity (slpar) read/write slpar scsi longitudinal parity [7:0] the scsi longitudinal parity (slpar) register consists of two multiplexed bytes; other register bit settings determine what is displayed at this memory location at any given time. when bit 5 in the scsi control two (scntl2) (slpmd) register is cleared, the chip xors the high and low bytes of the scsi longitudinal parity (slpar) register together to give a single-byte value which is displayed in the scsi longitudinal parity (slpar) register. if the slpmd bit is set, then the scsi longitudinal parity (slpar) register shows either the high byte or the low byte of the slpar word. the slpar high byte enable bit, scsi control two (scntl2) , bit 4, determines which byte of the scsi longitudinal parity (slpar) register is visible on the scsi longitudinal par- ity (slpar) register at any given time. if this bit is cleared, the scsi longitudinal parity (slpar) register contains the low byte of the slpar word; if it is set, the scsi longitudinal parity (slpar) register contains the high byte of the slpar word. this register performs a bytewise longitudinal parity check on all scsi data received or sent through the scsi core. if one of the bytes received or sent (usually the last) is the set of correct even parity bits, slpar should go to zero (assuming it started at zero). as an example, suppose that the following three data bytes and one check byte are received from the scsi bus (all signals are shown active high): 7 0 slpar xxxxxxxx operating registers 4-79 a one in any bit position of the ?nal slpar value would indicate a transmission error. the scsi longitudinal parity (slpar) register is also used to generate the check bytes for scsi send operations. if the scsi longitudinal parity (slpar) register contains all zeros prior to sending a block move, it contains the appropriate check byte at the end of the block move. this byte must then be sent across the scsi bus. note: writing any value to this register clears it to zero. the longitudinal parity checks are meant to provide an added measure of scsi data integrity and are entirely optional. this register does not latch scsi selection/reselection ids under any circumstances. the default value of this register is zero. register: 0x45 (0xc5) scsi wide residue (swide) read/write swide scsi wide residue [7:0] after a wide scsi data receive operation, this register contains a residual data byte if the last byte received was never sent across the dma bus. it represents either the ?rst data byte of a subsequent data transfer, or it is a residue byte which should be cleared when an ignore data bytes running slpar C 00000000 1. 11001100 11001100 (xor of word 1) 2. 01010101 10011001 (xor of word 1 and 2) 3. 00001111 10010110 (xor of word 1, 2 and 3) even parity >>> 10010110 4. 10010110 00000000 7 0 swide xxxxxxxx 4-80 registers wide residue message is received. it may also be an overrun data byte. the power-up value of this register is indeterminate. register: 0x46 (0xc6) memory access control (macntl) read/write typ[3:0] chip type [7:4] these bits identify the chip type for software purposes. this technical manual applies to devices that have these bits set to 0x06. bits 3 through 0 of this register are used to determine if an external bus master access is to local or far memory. when bits 3 through 0 are set, the corresponding access is considered local and the mac/_testout pin is driven high. when these bits are clear, the corresponding access is to far memory and the mac/_testout pin is driven low. this function is enabled after a transfer control scripts instruction is executed. dwr datawr 3 this bit is used to de?ne if a data write is considered local memory access. drd datard 2 this bit is used to de?ne if data write is considered local memory access. pscpt pointer scripts 1 this bit is used to de?ne if a pointer to a scripts indirect or table indirect fetch is considered local memory access. scpts scripts 0 this bit is used to de?ne if a scripts fetch is considered local memory access. 7 43210 typ[3:0] dwr drd pscpt scpts 01100000 operating registers 4-81 register: 0x47 (0xc7) general purpose pin control (gpcntl) read/write this register is used to determine if the pins controlled by the general purpose (gpreg) register are inputs or outputs. bits [4:0] in gpcntl correspond to bits [4:0] in the general purpose (gpreg) register. when the bits are enabled as inputs, an internal pull-up is also enabled. me master enable 7 the internal bus master signal is presented on gpio1 if this bit is set, regardless of the state of bit 1 (gpio1_en). fe fetch enable 6 the internal opcode fetch signal is presented on gpio0 if this bit is set, regardless of the state of bit 0 (gpio0_en). r reserved 5 gpio[4:2] gpio4_enCgpio2_en (gpio enable) [4:2] general purpose control bits, corresponding to bits [4:2] in the general purpose (gpreg) register and pins 60, 59, and 57. gpio4 powers up as a general purpose output, and gpio[3:2] power-up as general purpose inputs. gpio[1:0] gpio1_enCgpio0_en (gpio enable) [1:0] these bits power-up set, causing the gpio1 and gpio0 pins to become inputs. clearing these bits causes gpio[1:0] to become outputs. 7654 210 me fe r gpio[4:2] gpio[1:0] 00 x01111 4-82 registers register: 0x48 (0xc8) scsi timer zero (stime0) read/write hth[3:0] handshake-to-handshake timer period [7:4] these bits select the handshake-to-handshake time-out period, the maximum time between scsi handshakes (sreq/ to sreq/ in target mode, or sack/ to sack/ in the initiator mode). when this timing is exceeded, an interrupt is generated and the hth bit in the scsi interrupt status one (sist1) register is set. table 4.7 contains time-out periods for the handshake-to- handshake timer, the selection/reselection timer (bits [3:0]), and the general purpose timer ( scsi timer one (stime1), bits [3:0]). for a more detailed explanation of interrupts, refer to chapter 2, functional description. 743 0 hth[3:0] sel[3:0] 00000000 operating registers 4-83 sel[3:0] selection time-out [3:0] these bits select the scsi selection/reselection time-out period. when this timing (plus the 200 m s selection abort time) is exceeded, the sto bit in the scsi interrupt status one (sist1) register is set. for a more detailed explanation of interrupts, refer to chapter 2, functional description. table 4.7 timeout periods hth[7:4], sel[3:0], gen[3:0] 1 minimum timeout (40 or 160 mhz) minimum timeout (50 mhz) 0000 disabled disabled 0001 125 m s 100 m s 0010 250 m s 200 m s 0011 500 m s 400 m s 0100 1 ms 800 m s 0101 2 ms 1.6 ms 0110 4 ms 3.2 ms 0111 8 ms 6.4 ms 1000 16 ms 12.8 ms 1001 32 ms 25.6 ms 1010 64 ms 51.2 ms 1011 128 ms 102.4 ms 1100 256 ms 204.8 ms 1101 512 ms 409.6 ms 1110 1.024 s 819.2 ms 1111 2.048 s 1.6384 s 1. these values are correct if the ccf bits in the scsi control three (scntl3) register are set according to the valid combinations in the bit description. 4-84 registers register: 0x49 (0xc9) scsi timer one (stime1) read/write r reserved 7 hthba handshake-to-handshake timer bus activity enable 6 setting this bit causes this timer to begin testing for scsi req/ and ack/ activity as soon as sbsy/ is asserted, regardless of the agents participating in the transfer. gensf general purpose timer scale factor 5 setting this bit causes this timer to shift by a factor of 16. see table 4.8 for timeout periods, 50 mhz clock. 76543 0 r hthba gensf hthsf gen[3:0] x0000000 table 4.8 timeout periods, 50 mhz clock hth[7:4], sel[3:0], gen[3:0] 1 minimum timeout (50 mhz clock) 2 gensf = 0 gensf = 1 0000 disabled disabled 0001 100 m s 1.6 ms 0010 200 m s 3.2 ms 0011 400 m s 6.4 ms 0100 800 m s 12.8 ms 0101 1.6 ms 25.6 ms 0110 3.2 ms 51.2 ms 0111 6.4 ms 102.4 ms 1000 12.8 ms 204.8 ms 1001 25.6 ms 409.6 ms 1010 51.2 ms 819.2 ms 1011 102.4 ms 1.6 s 1100 204.8 ms 3.2 s operating registers 4-85 hthsf handshake-to-handshake timer scale factor 4 setting this bit causes this timer to shift by a factor of 16. refer to the scsi timer zero (stime0) register description for details. gen[3:0] general purpose timer period [3:0] these bits select the period of the general purpose timer. the time measured is the time between enabling and disabling of the timer. when this timing is exceeded, the gen bit in the scsi interrupt status one (sist1) register is set. refer to the table under scsi timer zero (stime0) , bits [3:0], for the available time-out periods. note: to reset a timer before it expires and obtain repeatable delays, the time value must be written to zero ?rst, and then written back to the desired value. this is also required when changing from one time value to another. see chapter 2, functional description, for an explanation of how interrupts are generated when the timers expire. 1101 409.6 ms 6.4 s 1110 819.2 ms 12.8 s 1111 1.6 s 25.6 s 1. these values are correct if the ccf bits in the scsi control three (scntl3) register are set according to the valid combinations in the bit description. 2. 50 mhz clock is not supported for ultra2 scsi operation. table 4.8 timeout periods, 50 mhz clock (cont.) hth[7:4], sel[3:0], gen[3:0] 1 minimum timeout (50 mhz clock) 2 gensf = 0 gensf = 1 4-86 registers register: 0x4a (0xca) response id zero (respid0) read/write respid0 response id zero [7:0] respid0 and response id one (respid1) contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most signi?cant bit of response id one (respid1) representing id 15 and the least signi?cant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the response id one (respid1) and response id zero (respid0) registers. however, the chip can arbitrate with only one id value in the scsi chip id (scid) register. register: 0x4b (0xcb) response id one (respid1) read/write respid1 response id one [15:8] respid0 and response id one (respid1) contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most signi?cant bit of response id one (respid1) representing id 15 and the least signi?cant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the response id one 7 0 id xxxxxxxx 15 8 id xxxxxxxx operating registers 4-87 (respid1) and response id zero (respid0) registers. however, the chip can arbitrate with only one id value in the scsi chip id (scid) register. register: 0x4c (0xcc) scsi test zero (stest0) read only ssaid[3:0] scsi selected as id [7:4] these bits contain the encoded value of the scsi id that the LSI53C825A is selected or reselected as during a scsi selection or reselection phase. these bits are read only and contain the encoded value of 0C15 possible ids that could be used to select the LSI53C825A. during a scsi selection or reselection phase when a valid id is put on the bus, and the LSI53C825A responds to that id, the selected as id is written into these bits. these bits are used with response id zero (respid0) and response id one (respid1) registers to allow response to multiple ids on the bus. slt selection response logic test 3 this bit is set when the LSI53C825A is ready to be selected or reselected. this does not take into account the bus settle delay of 400 ns. this bit is used for functional test and fault purposes. art arbitration priority encoder test 2 this bit is always set when the LSI53C825A exhibits the highest priority id asserted on the scsi bus during arbitration. it is primarily used for chip level testing, but it may be used during low level mode operation to determine if the LSI53C825A won arbitration. soz scsi synchronous offset zero 1 this bit indicates that the current synchronous sreq/, sack/ offset is zero. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set, the LSI53C825A scsi functioning as an initiator, is waiting for the target 7 43210 ssaid[3:0] slt art soz som 00000x11 4-88 registers to request data transfers. if the LSI53C825A scsi is functioning as a target, then the initiator has sent the offset number of acknowledges. som scsi synchronous offset maximum 0 this bit indicates that the current synchronous sreq/, sack/ offset is the maximum speci?ed by bits [3:0] in the scsi transfer (sxfer) register. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set, the LSI53C825A scsi is functioning as a target, and is waiting for the initiator to acknowledge the data transfers. if the LSI53C825A scsi is functioning as an initiator, then the target has sent the offset number of requests. register: 0x4d (0xcd) scsi test one (stest1) read/write sclk scsi clock 7 when set, this bit disables the external sclk (scsi clock) pin, and the chip uses the pci clock as the internal scsi clock. if a transfer rate of 10 mbytes/s (or 20 mbytes/s on a wide scsi bus) is desired on the scsi bus, this bit must be cleared and at least a 40 mhz external sclk must be provided. siso scsi isolation mode 6 this bit allows the LSI53C825A to put the scsi bidirectional and input pins into a low power mode when the scsi bus is not in use. when this bit is set, the scsi bus inputs are logically isolated from the scsi bus. r reserved [5:0] 765 0 sclk siso r 00 x x x x x x operating registers 4-89 register: 0x4e (0xce) scsi test two (stest2) read/write sce scsi control enable 7 setting this bit allows assertion of all scsi control and data lines through the scsi output control latch (socl) and scsi output data latch (sodl) registers regardless of whether the LSI53C825A is con?gured as a target or initiator. note: do not set this bit during normal operation, since it could cause contention on the scsi bus. it is included for diagnostic purposes only. rof reset scsi offset 6 setting this bit clears any outstanding synchronous sreq/sack offset. if a scsi gross error occurs, set this bit. this bit automatically clears itself after resetting the synchronous offset. dif scsi differential mode 5 setting this bit allows the LSI53C825A to interface properly to external differential transceivers. its only real effect is to 3-state the sbsy/, ssel/, and srst/ pads so that they can be used as pure inputs. clearing this bit enables se mode operation. this bit should be set in the initialization routine if the differential pair interface is used. slb scsi loopback mode 4 setting this bit allows the LSI53C825A to perform scsi loopback diagnostics. that is, it enables the scsi core to simultaneously perform as both the initiator and the target. 76543210 sce rof dif slb szm aws ext low 00000000 4-90 registers szm scsi high impedance mode 3 setting this bit places all the open drain 48 ma scsi drivers into a high impedance state. this is to allow internal loopback mode operation without affecting the scsi bus. aws always wide scsi 2 when this bit is set, all scsi information transfers are done in the 16-bit wide mode. this includes data, message, command, status, and reserved phases. normally, deassert this bit since 16-bit wide message, command, and status phases are not supported by the scsi speci?cations. ext extend sreq/sack/ filtering 1 lsi logic tolerant scsi receiver technology includes a special digital ?lter on the sreq/ and sack/ pins which causes the disregarding of glitches on deasserting edges. setting this bit increases the ?ltering period from 30 ns to 60 ns on the deasserting edge of the sreq/ and sack/ signals. note: never set this bit during fast scsi (greater than 5 mbytes transfers per second) operations, because a valid assertion could be treated as a glitch. low scsi low level mode 0 setting this bit places the LSI53C825A in low level mode. in this mode, no dma operations occur, and no scripts execute. arbitration and selection may be performed by setting the start sequence bit as described in the scsi control zero (scntl0) register. scsi bus transfers are performed by manually asserting and polling scsi signals. clearing this bit allows instructions to be executed in the scsi scripts mode. note: it is not necessary to set this bit for access to the scsi bit-level registers ( scsi output data latch (sodl) , scsi bus control lines (sbcl) , and input registers). operating registers 4-91 register: 0x4f (0xcf) scsi test three (stest3) read/write te tolerant enable 7 setting this bit enables the active negation portion of lsi logic tolerant technology. active negation causes the scsi request, acknowledge, data, and parity signals to be actively deasserted, instead of relying on external pull-ups, when the LSI53C825A is driving these signals. active deassertion of these signals occurs only when the LSI53C825A is in an information transfer phase. when operating in a differential environment or at fast scsi timings, tolerant active negation should be enabled to improve setup and deassertion times. active negation is disabled after reset or when this bit is cleared. for more information on lsi logic tolerant technology, see chapter 1, introduction. str scsi fifo test read 6 setting this bit places the scsi core into a test mode in which the scsi fifo is easily read. reading the least signi?cant byte of the scsi output data latch (sodl) register causes the fifo to unload. the functions are summarized in the following table. hsc halt scsi clock 5 asserting this bit causes the internal divided scsi clock to come to a stop in a glitchless manner. this bit is used for test purposes or to lower i dd during a power-down mode. 76543210 te str hsc dsi s16 ttm csf stw 00000000 register name register operation fifo bits fifo function sodl read [15:0] unload sodl0 read [7:0] unload sodl1 read [15:8] none 4-92 registers dsi disable single initiator response 4 if this bit is set, the LSI53C825A ignores all bus-initiated selection attempts that employ the single-initiator option from scsi-1. in order to select the LSI53C825A while this bit is set, the LSI53C825A scsi id and the initiators scsi id must both be asserted. assert this bit in scsi-2 systems so that a single bit error on the scsi bus is not interpreted as a single initiator response. s16 16-bit system 3 if this bit is set, all devices in the scsi system implementation are assumed to be 16-bit. this causes the LSI53C825A to always check the parity bit for scsi ids 15C8 during bus-initiated selection or reselection, assuming parity checking has been enabled. if an 8-bit scsi device attempts to select the LSI53C825A while this bit is set, the LSI53C825A ignores the selection attempt. this is because the parity bit for ids 15C8 are not driven. see the description of the enable parity checking bit in the scsi control zero (scntl0) register for more information. ttm timer test mode 2 asserting this bit facilitates testing of the selection time-out, general purpose, and handshake-to-handshake timers by greatly reducing all three time-out periods. setting this bit starts all three timers and if the respective bits in the scsi interrupt enable one (sien1) register are asserted, the LSI53C825A generates interrupts at time-out. this bit is intended for internal manufacturing diagnosis and should not be used. csf clear scsi fifo 1 setting this bit causes the full ?ags for the scsi fifo to be cleared. this empties the fifo. this bit is self-clearing. in addition to the scsi fifo pointers, the sidl, sodl, and sodr full bits in the scsi status zero (sstat0) and scsi status two (sstat2) are cleared. stw scsi fifo test write 0 setting this bit places the scsi core into a test mode in which the fifo is easily read or written. while this bit is set, writes to the least signi?cant byte of the scsi output operating registers 4-93 data latch (sodl) register cause the entire word contained in sodl to be loaded into the fifo. these functions are summarized in the following table. registers: 0x50C0x51 (0xd0C0xd1) scsi input data latch (sidl) read only sidl scsi input data latch [15:0] this register is used primarily for diagnostic testing, programmed i/o operation, or error recovery. data received from the scsi bus can be read from this register. data can be written to the scsi output data latch (sodl) register and then read back into the LSI53C825A by reading this register to allow loopback testing. when receiving scsi data, the data ?ows into this register and out to the host fifo. this register differs from the scsi bus data lines (sbdl) register; scsi input data latch (sidl) contains latched data and the scsi bus data lines (sbdl) always contains exactly what is currently on the scsi data bus. reading this register causes the scsi parity bit to be checked, and causes a parity error interrupt if the data is not valid. the power-up values are indeterminate. register name register operation fifo bits fifo function sodl write [15:0] unload sodl0 write [7:0] unload sodl1 write [15:8] none 15 0 sidl xxxxx x x x x xxx x xxx 4-94 registers registers: 0x54C0x55 (0xd4C0xd5) scsi output data latch (sodl) read/write sodl scsi output data latch [15:0] this register is used primarily for diagnostic testing or programmed i/o operation. data written to this register is asserted onto the scsi data bus by setting the assert data bus bit in the scsi control one (scntl1) register. this register is used to send data using programmed i/o. data ?ows through this register when sending data in any mode. it is also used to write to the synchronous data fifo when testing the chip. the power-up value of this register is indeterminate. registers: 0x58C0x59 (0xd8C0xd9) scsi bus data lines (sbdl) read only sbdl scsi bus data lines [15:0] this register contains the scsi data bus status. even though the scsi data bus is active low, these bits are active high. the signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read. this register is used when receiving data using programmed i/o. this register can also be used for diagnostic testing or in the low level mode. the power-up value of this register is indeterminate. if the chip is in the wide mode ( scsi control three (scntl3) , bit 3 and scsi test two (stest2) , bit 2 are set) and scsi bus data lines (sbdl) is read, both byte lanes are checked for parity regardless of phase. when in a nondata phase, this causes a parity error interrupt to be generated because upper byte lane parity is invalid. 15 0 sodl xxxxx x x x x xxx x xxx 15 0 sbdl xxxxx x x x x xxx x xxx operating registers 4-95 registers: 0x5cC0x5f (0xdcC0xdf) scratch register b (scratchb) read/write scratchb scratch register b [31:0] this is a general purpose user de?nable scratch pad register. apart from cpu access, only register read/write and memory moves directed at the scratch register alter its contents. the LSI53C825A cannot fetch scripts instructions from this location. when bit 3 in the chip test two (ctest2) register is set, this register contains the base address for the 4 kbyte internal ram. setting chip test two (ctest2), bit 3 only causes the base address to appear in the scratch register b (scratchb) register; any information that was previously in the register remains intact. any writes to this register while the bit is set passes through the actual scratch register b (scratchb) register. the power-up values are indeterminate. registers: 0x60C0x7f (0xe0C0xff) scratch registers cCj (scratchcCscratchj) read/write these registers are general purpose scratch registers for user de?ned functions. the LSI53C825A cannot fetch scripts instructions from this location. the power-up value of these registers is indeterminate. 31 0 scratchb xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 4-96 registers LSI53C825A/825ae pci to scsi i/o processor 5-1 chapter 5 scsi scripts instruction set after power-up and initialization of the LSI53C825A, the chip can be operated in the low level register interface mode or in the high level scsi scripts mode. chapter 5 is divided into the following sections: section 5.1, low level register interface mode section 5.2, high level scsi scripts mode section 5.3, block move instructions section 5.4, i/o instruction section 5.5, read/write instructions section 5.6, transfer control instructions section 5.7, memory move instructions section 5.8, load and store instructions 5.1 low level register interface mode with the low level register interface mode, the user has access to the dma control logic and the scsi bus control logic. an external processor has access to the scsi bus signals and the low level dma signals, which allows creation of complicated board level test algorithms. the low level interface is useful for backward compatibility with scsi devices that require certain unique timings or bus sequences to operate properly. another feature allowed at the low level is loopback testing. in loopback mode, the scsi core can be directed to talk to the dma core to test internal data paths all the way out to the chips pins. 5-2 scsi scripts instruction set 5.2 high level scsi scripts mode to operate in the scsi scripts mode, the LSI53C825A requires only a scripts start address. the start address must be at a dword (four byte) boundary to align all the following scripts at a dword boundary since all scripts are 8 or 12 bytes long. instructions are fetched until an interrupt instruction is encountered, or until an unexpected event (such as a hardware error) causes an interrupt to the external processor. once an interrupt is generated, the LSI53C825A halts all operations until the interrupt is serviced. then, the start address of the next scripts instruction may be written to the dma scripts pointer (dsp) register to restart the automatic fetching and execution of instructions. the scsi scripts mode of execution allows the LSI53C825A to make decisions based on the status of the scsi bus, which of?oads the microprocessor from servicing the numerous interrupts inherent in i/o operations. given the rich set of scsi-oriented features included in the instruction set, and the ability to re-enter the scsi algorithm at any point, this high level interface is all that is required for both normal and exception conditions. switching to low level mode for error recovery should never be required. high level scsi scripts mode 5-3 the following types of scripts instructions are implemented in the LSI53C825A, as shown in table 5.1 : each instruction consists of two or three 32-bit words. the ?rst 32-bit word is always loaded into the dma command (dcmd) and dma byte counter (dbc) registers, the second into the dma scripts pointer save (dsps) register. the third word, used only by memory move instructions, is loaded into the temporary (temp) shadow register. in an indirect i/o or move instruction, the ?rst two 32-bit opcode fetches is followed by one or two more 32-bit fetch cycles. 5.2.1 sample operation this sample operation describes execution of a scripts instruction for a block move instruction. the host cpu, through programmed i/o, gives the dma scripts pointer (dsp) register (in the operating register ?le) the starting address in main memory that points to a scsi scripts program for execution. table 5.1 scripts instructions instruction description block move block move instruction moves data between the scsi bus and memory. i/o or read/write i/o or read/write instructions cause the LSI53C825A to trigger common scsi hardware sequences, or to move registers. transfer control transfer control instruction allows scripts instructions to make decisions based on real time scsi bus conditions. memory move memory move instruction causes the LSI53C825A to execute block moves between different parts of main memory. load and store load and store instructions provide a more ef?cient way to move data to/from memory from/to an internal register in the chip without using the memory move instruction. 5-4 scsi scripts instruction set loading the dma scripts pointer (dsp) register causes the LSI53C825A to fetch its ?rst instruction at the address just loaded. this is from main memory or the internal ram, depending on the address. the LSI53C825A typically fetches two dwords (64 bits) and decodes the high-order byte of the ?rst longword as a scripts instruction. if the instruction is a block move, the lower three bytes of the ?rst longword are stored and interpreted as the number of bytes to be moved. the second longword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed. for a scsi send operation, the LSI53C825A waits until there is enough space in the dma fifo to transfer a programmable size block of data. for a scsi receive operation, it waits until enough data is collected in the dma fifo for transfer to memory. at this point, the LSI53C825A requests use of the pci bus again to transfer the data. when the LSI53C825A is granted the pci bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrement the internally stored remaining byte count, increment the address pointer, and then releases the pci bus. the LSI53C825A stays off the pci bus until the fifo can again hold (for a write) or has collected (for a read) enough data to repeat the process. the process repeats until the internally stored byte count has reached zero. the LSI53C825A releases the pci bus and then performs another scripts instruction fetch cycle, using the incremented stored address maintained in the dma scripts pointer (dsp) register. execution of scripts instructions continues until an error condition occurs or an interrupt scripts instruction is received. at this point, the LSI53C825A interrupts the host cpu and waits for further servicing by the host system. it can execute independent block move instructions specifying new byte counts and starting locations in main memory. in this manner, the LSI53C825A performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or requiring an external dma controller to be programmed. an overview of this process is presented in figure 5.1 . high level scsi scripts mode 5-5 figure 5.1 scripts overview system processor system memory scsi initiator write example select atn 0, alt_addr move from identify_msg_buf, when msg_out move from cmd_buf, when cmd move from data_buf when data_out move from stat_in_buf, when status move from msg_in_buf, when msg_in move scntl2 & 7f to scntl2 clear ack wail disconnect alt2 int 10 ta b l e byte count address byte count address byte count address byte count address message buffer command buffer data buffer status buffer s y s t e m write dsa write dsp fetch scripts data LSI53C825A scsi bus b u s 5-6 scsi scripts instruction set 5.3 block move instructions performing a block move instruction, bit 5, source i/o - memory enable (siom) and bit 4, destination i/o - memory enable (diom) in the dma mode (dmode) register determines whether the source/destination address resides in memory or i/o space. when data is being moved onto the scsi bus, siom controls whether that data comes from i/o or memory space. when data is being moved off of the scsi bus, diom controls whether that data goes to i/o or memory space. 5.3.1 first dword it[1:0] instruction type - block move [31:30] ia indirect addressing 29 when this bit is cleared, user data is moved to or from the 32-bit data start address for the block move instruction. the value is loaded into the chips address register and incremented as data is transferred. the address of the data to move is in the second dword of this instruction. when this bit is one, the 32-bit user data start address for the block move is the address of a pointer to the actual data buffer address. the value at the 32-bit start address is loaded into the chips dma next address (dnad) register using a third longword fetch (4-byte transfer across the host computer bus). direct addressing the byte count and absolute address are: indirect addressing use the fetched byte count, but fetch the data address from the address in the instruction. command byte count address of data command byte count address of pointer to data block move instructions 5-7 once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. this indirect feature allows a table of data buffer addresses to be speci?ed. using the lsi logic scsi scripts assembler, the table offset is placed in the script at compile time. then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor. the logical i/o driver builds a structure of addresses for an i/o rather than treating each address individually. this feature makes it possible to locate scsi scripts in a prom. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. tia table indirect 28 when this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the data structure address (dsa) register. both the transfer count and the source/ destination address are fetched from this location. use the signed integer offset in bits [23:0] of the second four bytes of the instruction, added to the value in the data structure address (dsa) register, to fetch ?rst the byte count and then the data address. the signed value is combined with the data structure base address to generate the physical address used to fetch values from the data structure. sign extended values of all ones for negative values are allowed, but bits [31:24] are ignored. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. figure 5.2 illustrates the block move instruction register. command not used dont care table offset 5-8 scsi scripts instruction set figure 5.2 block move instruction register prior to the start of an i/o, the data structure address (dsa) register should be loaded with the base address of the i/o data structure. the address may be any address on a longword boundary. after a table indirect opcode is fetched, the dsa is added to the 24-bit signed offset value from the opcode to generate the address of the required data; both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. for a move instruction, the 24-bit byte count is fetched from system memory. then the 32-bit physical address is brought into the LSI53C825A. execution of the move begins at this point. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register 24-bit block move byte counter i/o c/d msg/ opcode table indirect addressing indirect addressing (lsi53c700 family compatible) 0 - instruction type - block move 0 - instruction type - block move block move instructions 5-9 scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and may cross system segment boundaries. there are two restrictions on the placement of pointer data in system memory: the eight bytes of data in the move instruction must be contiguous, as shown below, and indirect data fetches are not available during execution of a memory-to-memory dma operation. opc opcode 27 this 1-bit opcode ?eld de?nes the type of block move (move) instruction to be performed in target and initiator mode. target mode in target mode, the opcode bit de?nes the following operations: these instructions perform the following steps: 1. the LSI53C825A veri?es that it is connected to the scsi bus as a target before executing this instruction. 2. the LSI53C825A asserts the scsi phase signals (smsg/, sc_d/, and si_o/) as de?ned by the phase field bits in the instruction. 3. if the instruction is for the command phase, the LSI53C825A receives the ?rst command byte and decodes its scsi group code. 00 byte count physical data address opc instruction de?ned 0move 1 chmov 5-10 scsi scripts instruction set C if the scsi group code is either group 0, group 1, group 2, or group 5, and if the vendor unique enhancement 1 (vue1) bit ( scsi control two (scntl2) , bit 1) is clear, then the LSI53C825A overwrites the dma byte counter (dbc) register with the length of the command descriptor block: 6, 10, or 12 bytes. C if the vendor unique enhancement 1 (vue1) bit ( scsi control two (scntl2) , bit 1) is set, the LSI53C825A receives the number of bytes in the byte count regardless of the group code. C if the vendor unique enhancement 1 bit is clear and group code is vendor unique, the LSI53C825A receives the number of bytes in the count. C if any other group code is received, the dma byte counter (dbc) register is not modi?ed and the LSI53C825A requests the number of bytes speci?ed in the dma byte counter (dbc) register. if the dma byte counter (dbc) register contains 0x000000, an illegal instruction interrupt is generated. 4. the LSI53C825A transfers the number of bytes speci?ed in the dma byte counter (dbc) register starting at the address speci?ed in the dma next address (dnad) register. if the opcode bit is set and a data transfer ends on an odd byte boundary, the LSI53C825A stores the last byte in the scsi wide residue (swide) register during a receive operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can be completed. 5. if the satn/ signal is asserted by the initiator or a parity error occurred during the transfer, the transfer can optionally be halted and an interrupt generated. the disable halt on parity error or atn bit in the scsi control one (scntl1) register controls whether the LSI53C825A halts on these conditions immediately, or waits until completion of the current move. block move instructions 5-11 initiator mode in target mode, the opcode bit de?nes the following operations: these instructions perform the following steps: 1. the LSI53C825A veri?es that it is connected to the scsi bus as an initiator before executing this instruction. 2. the LSI53C825A waits for an unserviced phase to occur. an unserviced phase is any phase (with sreq/ asserted) for which the LSI53C825A has not yet transferred data by responding with a sack/. 3. the LSI53C825A compares the scsi phase bits in the dma command (dcmd) register with the latched scsi phase lines stored in the scsi status one (sstat1) register. these phase lines are latched when sreq/ is asserted. 4. if the scsi phase bits match the value stored in the scsi scsi status one (sstat1) register, the LSI53C825A transfers the number of bytes speci?ed in the dma byte counter (dbc) register starting at the address pointed to by the dma next address (dnad) register. if the opcode bit is cleared and a data transfer ends on an odd byte boundary, the LSI53C825A stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output control latch (socl) register during a send operation. this byte is combined with the ?rst byte from the subsequent transfer so that a wide transfer can complete. opc instruction de?ned 0 chmov 1move 5-12 scsi scripts instruction set 5. if the scsi phase bits do not match the value stored in the scsi status one (sstat1) register, the LSI53C825A generates a phase mismatch interrupt and the instruction is not executed. 6. during a message-out phase, after the LSI53C825A has performed a select with attention (or satn/ is manually asserted with a set atn instruction), the LSI53C825A deasserts satn/ during the ?nal sreq/sack/ handshake. 7. when the LSI53C825A is performing a block move for message-in phase, it does not deassert the sack/ signal for the last sreq/sack/ handshake. clear the sack/ signal using the clear sack i/o instruction. scsip[2:0] scsi phase [26:24] this 3-bit ?eld de?nes the scsi information transfer phase. when the LSI53C825A operates in initiator mode, these bits are compared with the latched scsi phase bits in the scsi status one (sstat1) register. when the LSI53C825A operates in target mode, it asserts the phase de?ned in this ?eld. the following table describes the possible combinations and the corresponding scsi phase. tc[23:0] transfer counter [23:0] this 24-bit ?eld speci?es the number of data bytes to be moved between the LSI53C825A and system memory. the ?eld is stored in the dma byte counter (dbc) register. when the LSI53C825A transfers data to/from memory, the dma byte counter (dbc) register is msg c_d i_o scsi phase 0 0 0 data-out 0 0 1 data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in block move instructions 5-13 decremented by the number of bytes transferred. in addition, the dma next address (dnad) register is incremented by the number of bytes transferred. this process is repeated until the dma byte counter (dbc) register is decremented to zero. at this time, the LSI53C825A fetches the next instruction. if bit 28 is set, indicating table indirect addressing, this ?eld is not used. the byte count is instead fetched from a table pointed to by the data structure address (dsa) register. 5.3.2 second dword start address [31:0] this 32-bit ?eld speci?es the starting address of the data to move to/from memory. this ?eld is copied to the dma next address (dnad) register. when the LSI53C825A transfers data to or from memory, the dma next address (dnad) register is incremented by the number of bytes transferred. when bit 29 is set, indicating indirect addressing, this address is a pointer to an address in memory that points to the data location. when bit 28 is set, indicating table indirect addressing, the value in this ?eld is an offset into a table pointed to by the data structure address (dsa) . the table entry contains byte count and address information. 5-14 scsi scripts instruction set 5.4 i/o instruction i/o instructions perform the following scsi operations in target and initiator mode. these i/o operations are chosen with the opcode bits in the dma command (dcmd) register. this section describes these i/o operations. 5.4.1 first dword it[1:0] instruction type - i/o instruction [31:30] the it bit con?guration (01) de?nes an i/o instruction type. opc[2:0] opcode [29:27] the opcode bit con?gurations de?ne the i/o operation performed, but the opcode bit meanings change in target mode compared to initiator mode. opcode bit con?gurations (101, 110, and 111) are considered read/write instructions, and are described in section 5.5, read/write instructions. this section describes target mode operations. opc2 opc1 opc0 target mode initiator mode 0 0 0 reselect select 0 0 1 disconnect wait disconnect 0 1 0 wait select wait reselect 0 1 1 set set 1 0 0 clear clear i/o instruction 5-15 target mode reselect instruction 1. the LSI53C825A arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. if the LSI53C825A wins arbitration, it attempts to reselect the scsi device whose id is de?ned in the destination id ?eld of the instruction. once the LSI53C825A wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move on to the next instruction before the reselection completes. it continues executing scripts until a script that requires a response from the initiator is encountered. 3. if the LSI53C825A is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the LSI53C825A to initiator mode if it is reselected, or to target mode if it is selected. disconnect instruction the LSI53C825A disconnects from the scsi bus by deasserting all scsi signal outputs. opc2 opc1 opc0 instruction de?ned 0 0 0 reselect 0 0 1 disconnect 0 1 0 wait select 011 set 1 0 0 clear 5-16 scsi scripts instruction set wait select instruction 1. if the LSI53C825A is selected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 2. if reselected, the LSI53C825A fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the LSI53C825A to initiator mode when it is reselected. 3. if the cpu sets the sigp bit in the scsi status zero (sstat0) register, the LSI53C825A aborts the wait select instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. do not set sack/ or satn/ except for testing purposes. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the arithmetic logic unit (alu) is set. note: none of the signals are set on the scsi bus in target mode. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output control latch (socl) register. do not set sack/ or satn/ except for testing purposes. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. note: none of the signals are cleared on the scsi bus in the target mode. figure 5.3 illustrates the i/o instruction register. i/o instruction 5-17 figure 5.3 i/o instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register r rr r set/clear atn/ set/clear ack/ set/clear target mode set/clear carry encoded destination id 0 encoded destination id 1 encoded destination id 2 encoded destination id 3 reserved reserved reserved reserved select with atn/ table indirect mode relative address mode opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - i/o 0 - instruction type - i/o second 32-bit word of the i/o instruction 32-bit jump address 5-18 scsi scripts instruction set initiator mode select instruction 1. the LSI53C825A arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. 2. if the LSI53C825A wins arbitration, it attempts to select the scsi device whose id is de?ned in the destination id ?eld of the instruction. once the LSI53C825A wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move to the next instruction before the selection completes. it continues executing scripts until a script that requires a response from the target is encountered. 3. if the LSI53C825A is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the LSI53C825A to initiator mode if it is reselected, or to target mode if it is selected. 4. if the select with satn/ ?eld is set, the satn/ signal is asserted during the selection phase. wait disconnect instruction the LSI53C825A waits for the target to perform a legal disconnect from the scsi bus. a legal disconnect occurs when sbsy/ and ssel/ are inactive for a opc2 opc1 opc0 instruction de?ned 0 0 0 select 0 0 1 wait disconnect 0 1 0 wait reselect 0 1 1 set 1 0 0 clear i/o instruction 5-19 minimum of one bus free delay (400 ns), after the LSI53C825A receives a disconnect message or a command complete message. wait reselect instruction 1. if the LSI53C825A is selected before being reselected, it fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. manually set the LSI53C825A to target mode when it is selected. 2. if the LSI53C825A is reselected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 3. if the cpu sets the sigp bit in the interrupt status zero (istat0) register, the LSI53C825A aborts the wait reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address ?eld stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the alu is set. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output control latch (socl) register. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. ra relative addressing mode 26 when this bit is set, the 24-bit signed value in the dma next address (dnad) register is used as a relative displacement from the current dma scripts pointer (dsp) address. use this bit only in conjunction with the 5-20 scsi scripts instruction set select, reselect, wait select, and wait reselect instructions. the select and reselect instructions can contain an absolute alternate jump address or a relative transfer address. ti table indirect mode 25 when this bit is set, the 24-bit signed value in the dma byte counter (dbc) register is added to the value in the data structure address (dsa) register, and used as an offset relative to the value in the data structure address (dsa) register. the scsi control three (scntl3) value, scsi id, synchronous offset and synchronous period are loaded from this address. prior to the start of an i/o, load the data structure address (dsa) with the base address of the i/o data structure. any address on a dword boundary is allowed. after a table indirect opcode is fetched, the data structure address (dsa) is added to the 24-bit signed offset value from the opcode to generate the address of the required data. both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any dword boundary and may cross system segment boundaries. there are two restrictions on the placement of data in system memory: the i/o data structure must lie within the 8 mbytes above or below the base address. an i/o command structure must have all four bytes contiguous in system memory, as shown below. the offset/period bits are ordered as in the scsi transfer (sxfer) register. the con?guration bits are ordered as in the scsi control three (scntl3) register. con?g id offset/period 00 i/o instruction 5-21 use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. use bits 25 and 26 individually or in combination to produce the following conditions: direct uses the device id and physical address in the instruction. table indirect uses the physical jump address, but fetches data using the table indirect method. relative uses the device id in the instruction, but treats the alternate address as a relative jump. table relative treats the alternate jump address as a relative jump and fetches the device id, synchronous offset, and synchronous period indirectly. the value in bits [23:0] of bit 25 bit 26 addressing mode 0 0 direct 0 1 table indirect 1 0 relative 1 1 table relative command id not used not used absolute alternate address command table offset absolute alternate address command id not used not used absolute jump offset 5-22 scsi scripts instruction set the ?rst four bytes of the scripts instruction is added to the data structure base address to form the fetch address. sel select with atn/ 24 this bit speci?es whether satn/ is asserted during the selection phase when the LSI53C825A is executing a select instruction. when operating in initiator mode, set this bit for the select instruction. if this bit is set on any other i/o instruction, an illegal instruction interrupt is generated. r reserved [23:20] endid[3:0] encoded scsi destination id [19:16] this 4-bit ?eld speci?es the destination scsi id for an i/o instruction. r reserved [15:11] cc set/clear carry 10 this bit is used in conjunction with a set or clear instruction to set or clear the carry bit. setting this bit with a set instruction asserts the carry bit in the alu. clearing this bit with a clear instruction deasserts the carry bit in the alu. tm set/clear target mode 9 this bit is used in conjunction with a set or clear instruction to set or clear target mode. setting this bit with a set instruction con?gures the LSI53C825A as a target device (this sets bit 0 of the scsi control zero (scntl0) register). clearing this bit with a clear instruction con?gures the LSI53C825A as an initiator device (this clears bit 0 of the scsi control zero (scntl0) register). command table offset alternate jump offset i/o instruction 5-23 r reserved [8:7] ack set/clear sack/ 6 r reserved [5:4] atn set/clear satn/ 3 these two bits are used in conjunction with a set or clear instruction to assert or deassert the corresponding scsi control signal. bit 6 controls the scsi sack/ signal. bit 3 controls the scsi satn/ signal. the set instruction is used to assert sack/ and/or satn/ on the scsi bus. the clear instruction is used to deassert sack/ and/or satn/ on the scsi bus. the corresponding bit in the scsi output control latch (socl) register is set or cleared depending on the instruction used. since sack/ and satn/ are initiator signals, they are not asserted on the scsi bus unless the LSI53C825A is operating as an initiator or the scsi loopback enable bit is set in the scsi test two (stest2) register. the set/clear scsi ack/, atn/ instruction is used after message phase block move operations to give the initiator the opportunity to assert attention before acknowledging the last message byte. for example, if the initiator wishes to reject a message, it issues an assert scsi atn instruction before a clear scsi ack instruction. r reserved [2:0] 5.4.2 second dword sa start address [31:0] this 32-bit ?eld contains the memory address to fetch the next instruction if the selection or reselection fails. if relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current dma scripts pointer (dsp) register value. 5-24 scsi scripts instruction set 5.5 read/write instructions the read/write instruction supports addition, subtraction, and comparison of two separate values within the chip. it performs the desired operation on the speci?ed register and the scsi first byte received (sfbr) register, then stores the result back to the speci?ed register or the sfbr. 5.5.1 first dword it[1:0] instruction type - read/write instruction [31:30] the con?guration of the it bits, the opcode bits and the operator bits de?ne the read/write instruction type. the con?guration of all these bits determine which instruction is currently selected. figure 5.4 illustrates the read/write instruction register. read/write instructions 5-25 figure 5.4 read/write instruction register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register a0 a1 a2 a3 a4 a5 a6 use data8/sfbr operator 0 operator 1 operator 2 opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - r/w 0 - instruction type - r/w immediate data reserved (must be 0) register address 5-26 scsi scripts instruction set opc[2:0] opcode [29:27] the combinations of these bits determine if the instruction is a read/write or an i/o instruction. opcodes 0b000 through 0b100 are considered i/o instructions. o[2:0] operator [26:24] these bits are used in conjunction with the opcode bits to determine which instruction is currently selected. refer to table 5.1 for ?eld de?nitions. d8 use data8/sfbr 23 when this bit is set, scsi first byte received (sfbr) is used instead of the data8 value during a read-modify-write instruction (see table 5.1 ). this allows the user to add two register values. a[6:0] register address - a[6:0] [22:16] it is possible to change register values from scripts in read-modify-write cycles or move to/from scsi first byte received (sfbr) cycles. a[6:0] selects an 8-bit source/destination register within the LSI53C825A. immd immediate data [15:8] this 8-bit value is used as a second operand in logical and arithmetic functions. r reserved [7:0] 5.5.2 second dword destination address [31:0] this ?eld contains the 32-bit destination address where the data is to move. 5.5.3 read-modify-write cycles during these cycles the register is read, the selected operation is performed, and the result is written back to the source register. the add operation is used to increment or decrement register values (or memory values if used in conjunction with a memory-to-register move operation) for use as loop counters. read/write instructions 5-27 subtraction is not available when scsi first byte received (sfbr) is used instead of data8 in the instruction syntax. to subtract one value from another when using sfbr, ?rst xor the value to subtract (subtrahend) with 0xff, and add 1 to the resulting value. this creates the 2s complement of the subtrahend. the two values are then added to obtain the difference. 5.5.4 move to/from sfbr cycles all operations are read-modify-writes. however, two registers are involved, one of which is always the scsi first byte received (sfbr) . table 5.2 shows the possible read-modify-write operations. the possible functions of this instruction are: write one byte (value contained within the scripts instruction) into any chip register. move to/from the scsi first byte received (sfbr) from/to any other register. alter the value of a register with and, or, add, xor, shift left, or shift right operators. after moving values to the scsi first byte received (sfbr) , the compare and jump, call, or similar instructions are used to check the value. a move-to-sfbr followed by a move-from-sfbr is used to perform a register-to-register move. table 5.2 read/write instructions operator opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr 000 move data into register. syntax: move data8 to rega move data into scsi first byte received (sfbr) register. syntax: move data8 to sfbr move data into register. syntax: move data8 to rega 001 1 shift register one bit to the left and place the result in the same register. syntax: move rega shl rega shift register one bit to the left and place the result in the scsi first byte received (sfbr) register. syntax: move rega shl sfbr shift the scsi first byte received (sfbr) register one bit to the left and place the result in the register. syntax: move sfbr shl rega 5-28 scsi scripts instruction set miscellaneous notes: ? substitute the desired register name or address for rega in the syntax examples. ? data8 indicates eight bits of data. ? use scsi first byte received (sfbr) instead of data8 to add two register values. 010 or data with register and place the result in the same register. syntax: move rega | data8 to rega or data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega | data8 to sfbr or data with sfbr and place the result in the register. syntax: move sfbr | data8 to rega 011 xor data with register and place the result in the same register. syntax: move rega xor data8 to rega xor data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega xor data8 to sfbr xor data with sfbr and place the result in the register. syntax: move sfbr xor data8 to rega 100 and data with register and place the result in the same register. syntax: move rega & data8 to rega and data with register and place the result in the scsi first byte received (sfbr) register. syntax: move rega & data8 to sfbr and data with sfbr and place the result in the register. syntax: move sfbr & data8 to rega 101 1 shift register one bit to the right and place the result in the same register. syntax: move rega shr rega shift register one bit to the right and place the result in the scsi first byte received (sfbr) register. syntax: move rega shr sfbr shift the scsi first byte received (sfbr) register one bit to the right and place the result in the register. syntax: move sfbr shr rega 110 add data to register without carry and place the result in the same register. syntax: move rega + data8 to rega add data to register without carry and place the result in the scsi first byte received (sfbr) register. syntax: move rega + data8 to sfbr add data to sfbr without carry and place the result in the register. syntax: move sfbr + data8 to rega 111 add data to register with carry and place the result in the same register. syntax: move rega + data8 to rega with carry add data to register with carry and place the result in the scsi first byte received (sfbr) register. syntax: move rega + data8 to sfbr with carry add data to sfbr with carry and place the result in the register. syntax: move sfbr + data8 to rega with carry 1. data is shifted through the carry bit and the carry bit is shifted into the data byte. table 5.2 read/write instructions (cont.) operator opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr transfer control instructions 5-29 5.6 transfer control instructions this section describes the transfer control instructions. the con?guration of the opcode bits de?ne which transfer control instruction to perform. 5.6.1 first dword it[1:0] instruction type - transfer control instruction [31:30] the it bit con?guration (10) de?nes the transfer control instruction type. opc [2:0] opcode [29:27] this 3-bit ?eld speci?es the type of transfer control instruction to execute. all transfer control instructions can be conditional. they can be dependent on a true/false comparison of the alu carry bit or a comparison of the scsi information transfer phase with the phase ?eld, and/or a comparison of the first byte received with the data compare ?eld. each instruction can operate in initiator or target mode. transfer control instructions are shown in the following table. jump instruction the LSI53C825A can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, then it loads the scsi first byte received (sfbr) register with the contents of the dma scripts pointer save (dsps) register. the dma scripts pointer (dsp) register now contains the address of the next instruction. opc2 opc1 opc0 instruction de?ned 000jump 0 0 1 call 0 1 0 return 0 1 1 interrupt 1 x x reserved 5-30 scsi scripts instruction set if the comparisons are false, the LSI53C825A fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register, leaving the instruction pointer unchanged. call instruction the LSI53C825A can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register and that address value becomes the address of the next instruction. when the LSI53C825A executes a call instruction, the instruction pointer contained in the dma scripts pointer (dsp) register is stored in the temporary (temp) register. since the temporary (temp) register is not a stack and can only hold one dword, nested call instructions are not allowed. if the comparisons are false, the LSI53C825A fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modi?ed. figure 5.5 illustrates the transfer control instruction. transfer control instructions 5-31 figure 5.5 transfer control instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register wait for valid phase compare phase compare data jump if: true=1, false=0 interrupt on the fly carry test 0 (reserved) relative addressing mode i/o c/d msg opcode bit 0 opcode bit 1 opcode bit 2 1 - instruction type - transfer control 0 - instruction type - transfer control mask for compare data to be compared with the scsi first byte received 5-32 scsi scripts instruction set return instruction the LSI53C825A can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. that address value becomes the address of the next instruction. when a return instruction is executed, the value stored in the temporary (temp) register is returned to the dma scripts pointer (dsp) register. the LSI53C825A does not check to see whether the call instruction has already been executed. it does not generate an interrupt if a return instruction is executed without previously executing a call instruction. if the comparisons are false, the LSI53C825A fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register and the instruction pointer is not modi?ed. interrupt instruction the LSI53C825A can do a true/false comparison of the alu carry bit, or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, the LSI53C825A generates an interrupt by asserting the irq/ signal. the 32-bit address ?eld stored in the dma scripts pointer save (dsps) register can contain a unique interrupt service vector. when servicing the interrupt, this unique status code allows the interrupt service routine to quickly identify the point at which the interrupt occurred. the LSI53C825A halts and the dma scripts pointer (dsp) register must be written to before starting any further operation. transfer control instructions 5-33 interrupt-on-the-fly instruction the LSI53C825A can do a true/false comparison of the alu carry bit or compare the phase and/or data as de?ned by the phase compare, data compare, and true/false bit ?elds. if the comparisons are true, and the interrupt-on-the-fly bit ( interrupt status (istat) , bit 2) is set, the LSI53C825A asserts the interrupt-on-the-fly bit. scsip[2:0] scsi phase [26:24] this 3-bit ?eld corresponds to the three scsi bus phase signals that are compared with the phase lines latched when sreq/ is asserted. comparisons can be performed to determine the scsi phase actually being driven on the scsi bus. the following table describes the possible combinations and their corresponding scsi phase. these bits are only valid when the LSI53C825A is operating in initiator mode. clear these bits when the LSI53C825A is operating in target mode. ra relative addressing mode 23 when this bit is set, the 24-bit signed value in the dma scripts pointer save (dsps) register is used as a relative offset from the current dma scripts pointer (dsp) address (which is pointing to the next instruction, not the one currently executing). the relative mode does not apply to return and interrupt scripts. msg c/d i/o scsi phase 0 0 0 data-out 0 0 1 data-in 0 1 0 command 0 1 1 status 1 0 0 reserved-out 1 0 1 reserved-in 1 1 0 message-out 1 1 1 message-in 5-34 scsi scripts instruction set jump/call an absolute address start execution at the new absolute address. jump/call a relative address start execution at the current address plus (or minus) the relative offset. the scripts program counter is a 32-bit value pointing to the scripts currently under execution by the LSI53C825A. the next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the jump or call instruction. because it is signed (2s complement), the jump can be forward or backward. a relative transfer can be to any address within a 16 mbyte segment. the program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. scripts programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing scripts. for example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. if a script is written using only relative transfers it does not require any run time alteration of physical addresses, and can be stored in and executed from a prom. ct carry test 21 when this bit is set, decisions based on the alu carry bit can be made. true/false comparisons are legal, but data compare and phase compare are illegal. command condition codes absolute alternate address command condition codes dont care alternate jump offset transfer control instructions 5-35 if interrupt-on-the-fly 20 when this bit is set, the interrupt instruction does not halt the scripts processor. once the interrupt occurs, the interrupt-on-the-fly bit ( interrupt status (istat) , bit 2) is asserted. jmp jump if true/false 19 this bit determines whether the LSI53C825A branches when a comparison is true or when a comparison is false. this bit applies to phase compares, data compares, and carry tests. if both the phase compare and data compare bits are set, then both compares must be true to branch on a true condition. both compares must be false to branch on a false condition. cd compare data 18 when this bit is set, the ?rst byte received from the scsi data bus (contained in the scsi first byte received (sfbr) register) is compared with the data to be compared field in the transfer control instruction. the wait for valid phase bit controls when this compare occurs. the jump if true/false bit determines the condition (true or false) to branch on. cp compare phase 17 when the LSI53C825A is in initiator mode, this bit controls phase compare operations. when this bit is set, the scsi phase signals (latched by sreq/) are compared to the phase field in the transfer control instruction. if they match, the comparison is true. the wait for valid phase bit controls when the compare occurs. when the LSI53C825A is operating in target mode and this bit is set, it tests for an active scsi satn/ signal. bit 19 result of compare action 0 false jump taken 0 true no jump 1 false no jump 1 true jump taken 5-36 scsi scripts instruction set wvp wait for valid phase 16 if the wait for valid phase bit is set, the LSI53C825A waits for a previously unserviced phase before comparing the scsi phase and data. if the wait for valid phase bit is cleared, the LSI53C825A compares the scsi phase and data immediately. dcm data compare mask [15:8] the data compare mask allows a script to test certain bits within a data byte. during the data compare, if any mask bits are set, the corresponding bit in the scsi first byte received (sfbr) data byte is ignored. for instance, a mask of 0b01111111 and data compare value of 0b1xxxxxxx allows the scripts processor to determine whether or not the high order bit is set while ignoring the remaining bits. dcv data compare value [7:0] this 8-bit ?eld is the data compared against the register. these bits are used in conjunction with the data compare mask field to test for a particular data value. 5.6.2 second dword jump address [31:0] this 32-bit ?eld contains the address of the next instruction to fetch when a jump is taken. once the LSI53C825A fetches the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the dma scripts pointer (dsp) register and becomes the current instruction pointer. 5.7 memory move instructions for memory move instructions, bits 5 and 4 (siom and diom) in the dma mode (dmode) register determine whether the source or destination addresses reside in memory or i/o space. by setting these bits appropriately, data may be moved within memory space, within i/o space, or between the two address spaces. the memory move instruction is used to copy the speci?ed number of bytes from the source address to the destination address. memory move instructions 5-37 allowing the LSI53C825A to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current dma controllers. up to 16 mbytes may be transferred with one instruction. there are two restrictions: both the source and destination addresses must start with the same address alignment a[1:0]. if the source and destination are not aligned, then an illegal instruction interrupt occurs. for the pci cache line size register setting to take effect, the source and destination must be the same distance from a cache line boundary. indirect addresses are not allowed. a burst of data is fetched from the source address, put into the dma fifo and then written out to the destination address. the move continues until the byte count decrements to zero, then another scripts is fetched from system memory. the dma scripts pointer save (dsps) and data structure address (dsa) registers are additional holding registers used during the memory move. however, the contents of the data structure address (dsa) register are preserved. 5.7.1 first dword it[2:0] instruction type - memory move [31:29] the it bit con?guration (110) de?nes a memory move instruction type. r reserved [28:25] these bits are reserved and must be zero. if any of these bits are set, an illegal instruction interrupt occurs. nf no flush 24 when this bit is set, the LSI53C825A performs a memory move without ?ushing the prefetch unit. when this bit is cleared, the memory move instruction automatically ?ushes the prefetch unit. use the no flush option if the source and destination are not within four instructions of the current memory move instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2 . 5-38 scsi scripts instruction set tc[23:0] transfer counter [23:0] the number of bytes to transfer is stored in the lower 24 bits of the ?rst instruction word. 5.7.2 read/write system memory from scripts by using the memory move instruction, single or multiple register values are transferred to or from system memory. because the LSI53C825A responds to addresses as de?ned in the base address zero (i/o) or base address one (memory) registers, it can be accessed during a memory move operation if the source or destination address decodes to within the chips register space. if this occurs, the register indicated by the lower seven bits of the address is taken as the data source or destination. in this way, register values are saved to system memory and later restored, and scripts can make decisions based on data values in system memory. the scsi first byte received (sfbr) is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with a byte stored in system memory, ?rst move the byte to an intermediate LSI53C825A register (for example, a scratch register), and then to the scsi first byte received (sfbr) . the same address alignment restrictions apply to register access operations as to normal memory-to-memory transfers. 5.7.3 second dword dsps register [31:0] these bits contain the source address of the memory move. 5.7.4 third dword temp register [31:0] these bits contain the destination address for the memory move. figure 5.6 illustrates the memory move instruction. memory move instructions 5-39 figure 5.6 memory move instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register dcmd register dbc register 24-bit memory move byte counter no flush 0 (reserved) 0 (reserved) 0 (reserved) 0 (reserved) 0 - instruction type - memory move 1 - instruction type - memory move 1 - instruction type - memory move 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 temp register 5-40 scsi scripts instruction set 5.8 load and store instructions the load and store instructions provide a more ef?cient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. the load and store instructions are represented by two dword opcodes. the ?rst dword contains the dma command (dcmd) and dma byte counter (dbc) register values. the second dword contains the dma scripts pointer save (dsps) value. this is either the actual memory location of where to load and store, or the offset from the data structure address (dsa) , depending on the value of bit 28 (dsa relative). a maximum of 4 bytes may be moved with these instructions. the register address and memory address must have the same byte alignment, and the count set such that it does not cross dword boundaries. the memory address may not map back to the chip, excluding ram and rom. if it does, a pci read/write cycle occurs (the data does not actually transfer to/from the chip), and the chip issues an interrupt (illegal instruction detected) immediately following. the siom and diom bits in the dma mode (dmode) register determine whether the destination or source address of the instruction is in memory space or i/o space, as illustrated in the following table. the load and store utilizes the pci commands for i/o read and i/o write to access the i/o space. bit a1 bit a0 number of bytes allowed to load and store 0 0 one, two, three or four 0 1 one, two, or three 1 0 one or two 1 1 one bit source destination siom (load) memory register diom (store) register memory load and store instructions 5-41 5.8.1 first dword it[2:0] instruction type [31:29] these bits should be 0b111, indicating the load and store instruction. dsa dsa relative 28 when this bit is cleared, the value in the dma scripts pointer save (dsps) is the actual 32-bit memory address used to perform the load and store to/from. when this bit is set, the chip determines the memory address to perform the load and store to/from by adding the 24-bit signed offset value in the dma scripts pointer save (dsps) to the data structure address (dsa) . r reserved [27:26] nf no flush (store instruction only) 25 when this bit is set, the LSI53C825A performs a store without ?ushing the prefetch unit. when this bit is cleared, the store instruction automatically ?ushes the prefetch unit. use no flush if the source and destination are not within four instructions of the current store instruction. this bit has no effect on the load instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. ls load and store 24 when this bit is set, the instruction is a load. when cleared, it is a store. r reserved [23] ra[6:0] register address [22:16] a[6:0] selects the register to load and store to/from within the LSI53C825A. note: it is not possible to load the scsi first byte received (sfbr) register, although it is possible to store the sfbr contents to another location. r reserved [15:3] bc byte count [2:0] this value is the number of bytes to load and store. 5-42 scsi scripts instruction set 5.8.2 second dword memory i/o address / dsa offset [31:0] this is the actual memory location of where to load and store, or the offset from the data structure address (dsa) register value. figure 5.7 illustrates the load and store instruction format. load and store instructions 5-43 figure 5.7 load and store instruction format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsps register - memory/ i/o address/dsa offset dcmd register dbc register a0 a1 a2 a3 a4 a5 a6 0 (reserved) load/store no flush 0 - reserved 0 - reserved dsa relative 1 1 1 register address instruction type - load and store reserved (must be 0) byte count (number of bytes to load/store) 5-44 scsi scripts instruction set LSI53C825A/825ae pci to scsi i/o processor 6-1 chapter 6 speci?cations this chapter speci?es the LSI53C825A electrical and mechanical characteristics. it is divided into the following sections: section 6.1, dc characteristics section 6.2, tolerant technology electrical characteristics section 6.3, ac characteristics section 6.4, pci and external memory interface timing diagrams section 6.5, pci and external memory interface timing section 6.6, scsi timing diagrams section 6.7, package drawings 6.1 dc characteristics this section describes the LSI53C825A dc characteristics. table 6.1 through table 6.14 give current and voltage speci?cations. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operating conditions section of the manual is not implied. 6-2 speci?cations table 6.1 absolute maximum stress ratings symbol parameter min max unit test conditions t stg storage temperature - 55 150 cC v dd supply voltage - 0.5 7.0 v C v in input voltage v ss - 0.5 v dd +0.5 v C i lp 1 1. - 2v 6-4 speci?cations table 6.6 capacitance symbol parameter min max unit test conditions c i input capacitance of input pads C 7 pf C c io input capacitance of i/o pads C 10 pf C table 6.7 output signals 1 mac/_testout, req/ 1. req/ has a 100 m a pull-up that is enabled when testin is low. symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v - 16 ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 10 10 m aC table 6.8 output signals 1 irq/, sdir[15:0], sdirp0, sdirp1, bsydir, seldir, rstdir, tgs, igs, mas/[1:0], mce/, moe/, mwe/ 1. irq/, mas/[1:0], mce/, moe/, and mwe/ have a 100 m a pull-up that is enabled when testin is low. irq/ can be enabled with a register as an open drain with an internal 100 m a pull-up. symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v - 4ma 2 2. for irq/, test conditions are 8 ma. v ol output low voltage v ss 0.4 v 4 ma 2 i oz 3-state leakage - 10 10 m aC table 6.9 output signalserr/ symbol parameter min max unit test conditions v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 10 10 m aC dc characteristics 6-5 table 6.10 bidirectional signals 1 ad[31:0], c_be[3:0], frame/, irdy/, trdy/, devsel/, stop/, perr/, par/ symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v C v il input low voltage v ss - 0.5 0.8 v C v oh output high voltage 2.4 v dd v16ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 10 10 m aC 1. all the signals in this table have 25 m a pull-ups that are enabled when testin is low. table 6.11 bidirectional signals 1 gpio0_fetch/, gpio1_master/, gpio2_mas2/, gpio3, gpio4 symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v C v il input low voltage v ss - 0.5 0.8 v C v oh output high voltage 2.4 v dd v - 16 ma v ol output low voltage v ss 0.4 v 16 ma i oz 3-state leakage - 10 10 m aC 1. all the signals in this table have 100 m a pull-ups that are enabled when testin is low. 6-6 speci?cations table 6.12 bidirectional signals 1 mad[7:0] 1. all the signals in this table have 100 m a pull-ups that are enabled when testin is low. symbol parameter min max unit test conditions v ih input high voltage 2.0 v dd +0.5 v C v ih input high voltage - external memory pull-downs 3.85 v dd +0.5 v C v il input low voltage v ss - 0.5 0.8 v C v il input low voltage - external memory pull-downs v ss - 0.5 1.35 v C v oh output high voltage 2.4 v dd v - 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage - 10 10 m aC table 6.13 input signalstdi, tms, tck (LSI53C825Aj only) symbol parameter min max unit test conditions v ih input high voltage 3.85 v dd +0.5 v C v il input low voltage v ss - 0.5 1.35 v C i in input leakage - 800 - 200 m aC table 6.14 output signaltdo (LSI53C825Aj only) symbol parameter min max unit test conditions v oh output high voltage v dd - 0.5 v dd v - 4ma v ol output low voltage v ss 0.5 v 4 ma i oz 3-state leakage - 10 10 m aC tolerant technology electrical characteristics 6-7 6.2 tolerant technology electrical characteristics the LSI53C825A features tolerant technology, which includes active negation on the scsi drivers and input signal ?ltering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. table 6.15 provides electrical characteristics for se scsi signals. figure 6.1 through figure 6.5 provide reference information for testing scsi signals. 6-8 speci?cations table 6.15 tolerant technology electrical characteristics symbol parameter min max unit test conditions v oh 1 1. active negation outputs only: data, parity, sreq/, sack/. output high voltage 2.5 3.5 v i oh = 2.5 ma v ol output low voltage 0.1 0.5 v i ol =48ma v ih input high voltage 2.0 7.0 v C v il input low voltage - 0.5 0.8 v referenced to v ss v ik input clamp voltage - 0.66 - 0.77 v v dd = 4.75; i i = - 20 ma v th threshold, high to low 1.1 1.3 v C v tl threshold, low to high 1.5 1.7 v C v th Cv tl hysteresis 200 400 mv C i oh 1 output high current 2.5 24 ma v oh = 2.5 v i ol output low current 100 200 ma v ol = 0.5 v i osh 1 short-circuit output high current C 625 ma output driving low, pin shorted to v dd supply 2 2. single pin only; irreversible damage may occur if sustained for one second. i osl short-circuit output low current C 95 ma output driving high, pin shorted to v ss supply i lh input high leakage C 10 m a - 0.5 < v dd < 5.25 v pin = 2.7 v i ll input low leakage C - 10 m a - 0.5 < v dd < 5.25 v pin = 0.5 v r i input resistance 20 C m w scsi pins 3 3. scsi reset pin has 10 k w pull-up resistor. note: these values are guaranteed by periodic characterization; they are not 100% tested on every device. c p capacitance per pin C 10 pf pqfp t r 1 rise time, 10% to 90% 9.7 18.5 ns figure 6.1 t f fall time, 90% to 10% 5.2 14.7 ns figure 6.1 dv h /dt slew rate, low to high 0.15 0.49 v/ns figure 6.1 dv l /dt slew rate, high to low 0.19 0.67 v/ns figure 6.1 esd electrostatic discharge 2 C kv mil-std-883c; 3015-7 latch-up 100 C ma C filter delay 20 30 ns figure 6.2 extended ?lter delay 40 60 ns figure 6.2 tolerant technology electrical characteristics 6-9 figure 6.1 rise and fall time test conditions figure 6.2 scsi input filtering figure 6.3 hysteresis of scsi receivers 2.5 v 47 w 20 pf + - req/ or ack/ input t 1 v th note: t 1 is the input ?ltering period. 1 receiving logic level 0 1.1 1.3 1.5 1.7 input voltage (volts) 6-10 speci?cations figure 6.4 input current as a function of input voltage figure 6.5 output current as a function of output voltage +40 +20 0 - 20 - 40 - 4 0 4 8 12 16 - 0.7 v 8.2 v high-z output active input voltage (volts) input current (milliamperes) 14.4 v output sink current (milliamperes) - 800 - 600 - 400 - 200 0 012345 output voltage (volts) output source current (milliamperes) 20 40 60 80 100 012345 output voltage (volts) 0 ac characteristics 6-11 6.3 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to the section 6.1, dc characteristics ). chip timings are based on simulation at worst case voltage, temperature, and processing. timing was developed with a load capacitance of 50 pf. table 6.16 and figure 6.6 provide external clock timing data. figure 6.6 external clock table 6.16 external clock symbol parameter min max unit t 1 bus clock cycle time 30 dc ns scsi clock cycle time (sclk) 1 1. this parameter must be met to ensure scsi timings are within speci?cation. 12.5 60 ns t 2 clk low time 2 2. duty cycle not to exceed 60/40. 12 C ns sclk low time 2 5Cns t 3 clk high time 2 12 C ns sclk high time 2 5Cns t 4 clk slew rate 1 C v/ns sclk slew rate 1 C v/ns clk, sclk t 1 t 3 t 4 t 2 6-12 speci?cations table 6.17 and figure 6.7 provide reset input timing data. figure 6.7 reset input table 6.17 reset input symbol parameter min max unit t 1 reset pulse width 10 C t clk t 2 reset deasserted setup to clk high 0 C ns t 3 mad setup time to clk high (for con?guring the mad bus only) 20 C ns t 4 mad hold time from clk high (for con?guring the mad bus only) 20 C ns t 2 1. when enabled. clk rst/ mad 1 valid data t 3 t 4 t 1 pci and external memory interface timing diagrams 6-13 table 6.18 and figure 6.8 provide interrupt output timing data. figure 6.8 interrupt output 6.4 pci and external memory interface timing diagrams figure 6.9 through figure 6.30 represent signal activity when the LSI53C825A accesses the pci bus. the timings for the pci and external memory buses are listed on page 6-44 . this section includes timing diagrams for access to three groups of external memory con?gurations. the ?rst group applies to systems with memory size of 64 kbytes and above; one byte read or write cycle, and fast or normal roms. the second group applies to systems with memory size of 64 kbytes and above, one byte ready or write cycles, and slow roms. the third group applies to systems with memory size of 64 kbytes or less, one byte read or write cycles, and normal or fast rom. note: multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each additional byte. timing diagrams included in this section are: target timing C pci con?guration register read table 6.18 interrupt output symbol parameter min max unit t 1 clk high to irq/ low 20 C ns t 2 clk high to irq/ high 40 C ns t 3 irq/ deassertion time 3 C clk clk irq/ t 3 t 1 t 2 6-14 speci?cations C pci con?guration register write C operating register/scripts ram read C operating register/scripts ram write C external memory read C external memory write initiator timing C nonburst opcode fetch C burst opcode fetch C back-to-back read C back-to-back write C burst read C burst write external memory timing C read cycle, normal/fast memory ( 3 64 kbytes), single byte access C write cycle, normal/fast memory ( 3 64 kbytes), single byte access C read cycle, normal/fast memory ( 3 64 kbytes), multiple byte access C write cycle, normal/fast memory ( 3 64 kbytes), multiple byte access C read cycle, slow memory ( 3 64 kbytes) C write cycle, slow memory ( 3 64 kbytes) C read cycle, normal/fast memory ( 3 64 kbytes) C write cycle, normal/fast memory ( 3 64 kbytes) C read cycle, slow memory ( 64 kbytes) C write cycle, slow memory ( 64 kbytes) pci and external memory interface timing diagrams 6-15 6.4.1 target timing figure 6.9 through figure 6.14 describe target timing. figure 6.9 pci con?guration register read data out byte enable t 2 in out t 1 t 2 t 1 t 3 t 2 t 1 t 1 t 2 t 2 t 3 t 3 t 2 t 1 t 3 t 2 t 1 clk (driven by system) frame/ (driven by system) c_be/ (driven by master) pa r (driven by master-addr; LSI53C825A-data) irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) idsel (driven by master) cmd addr in ad/ (driven by master-addr; LSI53C825A-data) 6-16 speci?cations figure 6.10 pci con?guration register write t 1 t 2 clk (driven by system) frame/ (driven by master) addr in data in byte enable t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 t 2 t 1 ad/ (driven by master) c_be/ (driven by master) par/ (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) idsel (driven by master) t 1 t 2 cmd pci and external memory interface timing diagrams 6-17 figure 6.11 operating register/scripts ram read data byte enable t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad/ (driven by master-addr; c_be/ (driven by master) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) out t 3 in out t 3 LSI53C825A-data) LSI53C825A-data) cmd t 3 addr in 6-18 speci?cations figure 6.12 operating register/scripts ram write byte enable cmd t 2 t 1 t 2 t 1 t 2 t 1 t 1 t 2 t 2 t 3 t 2 t 1 t 3 clk (driven by system) frame/ (driven by master) ad/ (driven by master) c_be/ (driven by master) par/ (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) t 2 data in t 1 t 2 t 1 addr in pci and external memory interface timing diagrams 6-19 this page intentionally left blank. 6-20 speci?cations figure 6.13 external memory read clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) ad/ (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) data driven by memory) 1234 56 78910 LSI53C825A-data) byte enable LSI53C825A-data) mad (addr driven by LSI53C825A ; high order address middle order address low order address gpio2_mas2/ (driven by LSI53C825A) mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) t 1 t 2 t 1 t 2 cmd in t 1 t 2 t 1 t 2 t 1 t 3 t 13 t 11 t 12 moe/ (driven by LSI53C825A) addr in pci and external memory interface timing diagrams 6-21 figure 6.13 external memory read (cont.) clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) ad/ (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) data driven by memory) 11 12 13 14 15 16 17 18 19 20 LSI53C825A-data) LSI53C825A-data) mad (addr driven by LSI53C825A ; gpio2_mas2/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) t 3 t 2 t 2 t 15 21 t 3 out t 3 t 3 data in t 19 t 17 t 14 t 16 mas1/ (driven by LSI53C825A) data out 6-22 speci?cations figure 6.14 external memory write clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) ad (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) 1234 56 78910 LSI53C825A-data) byte enable LSI53C825A-data) mad (driven by LSI53C825A) high order address middle order address low order address gpio2_mas2/ (driven by LSI53C825A) mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) t 1 t 2 t 1 t 2 in t 1 t 2 t 1 t 2 t 1 t 3 t 13 t 11 t 12 data in t 23 t 20 t 1 addr in cmd mwe/ (driven by LSI53C825A) pci and external memory interface timing diagrams 6-23 figure 6.14 external memory write (cont.) clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) ad (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) LSI53C825A-data) LSI53C825A-data) mad (driven by LSI53C825A) mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) t 2 t 2 t 2 t 1 t 3 t 3 t 24 t 22 data in byte enable in data out t 25 t 26 t 21 t 20 t 23 t 2 gpio2_mas2/ (driven by LSI53C825A) 11 12 13 14 15 16 17 18 19 20 21 6-24 speci?cations 6.4.2 initiator timing figure 6.15 through figure 6.20 describe LSI53C825A initiator timing. figure 6.15 nonburst opcode fetch clk (driven by system) frame/ (driven by LSI53C825A) ad/ (driven by LSI53C825A- c_be/ (driven by LSI53C825A) par/ (driven by LSI53C825A- irdy/ (driven by LSI53C825A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) addr/ target-data) addr; target-data) gnt/ (driven by arbiter) req/ (driven by LSI53C825A) gpio1_master/ (driven by LSI53C825A) gpio0_fetch/ (driven by LSI53C825A) addr out addr out cmd be be cmd t 1 t 2 t 3 t 10 t 8 t 7 t 9 t 4 t 6 t 5 t 1 t 1 t 1 t 2 t 2 t 2 t 3 t 3 t 3 t 3 t 3 data in data in pci and external memory interface timing diagrams 6-25 figure 6.16 burst opcode fetch clk (driven by system) frame/ (driven by LSI53C825A) ad/ (driven by LSI53C825A- c_be/ (driven by LSI53C825A) pa r (driven by LSI53C825A- irdy/ (driven by LSI53C825A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) addr; target-data) addr; target-data) gnt/ (driven by arbiter) req/ (driven by LSI53C825A) gpio1_master/ (driven by LSI53C825A) gpio0_fetch/ (driven by LSI53C825A) t 7 t 8 t 9 t 10 t 6 t 5 t 4 t 3 t 2 t 1 in be cmd addr out out in t 3 t 3 t 3 t 3 t 3 t 3 t 2 t 2 t 2 t 1 t 1 t 1 data in data in 6-26 speci?cations figure 6.17 back-to-back read clk (driven by system) frame/ (driven by LSI53C825A) ad/ (driven by LSI53C825A- c_be/ (driven by LSI53C825A) pa r (driven by LSI53C825A- irdy/ (driven by LSI53C825A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) addr; target-data ) addr; target-data) gnt/ (driven by arbiter) req/ (driven by LSI53C825A) gpio1_master/ (driven by LSI53C825A) gpio0_fetch/ (driven by LSI53C825A ) in cmd t 9 data in in out t 6 t 5 t 3 t 4 t 3 t 3 t 3 t 3 t 1 t 2 t 2 t 1 t 2 t 1 t 2 t 10 t 1 data in out be cmd be addr out addr out pci and external memory interface timing diagrams 6-27 figure 6.18 back-to-back write clk (driven by system) frame/ (driven by LSI53C825A) ad/ (driven by LSI53C825A) c_be/ (driven by LSI53C825A) par/ (driven by LSI53C825A) irdy/ (driven by 53c825a) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) gnt/ (driven by arbiter) req/ (driven by LSI53C825A) gpio1_master/ (driven by LSI53C825A) gpio0_fetch/ (driven by LSI53C825A) t 3 t 2 t 4 t 1 t 5 t 6 t 9 t 10 addr out data out cmd be addr out data out cmd be t 3 t 3 t 3 t 3 t 3 t 3 t 1 t 2 t 3 6-28 speci?cations figure 6.19 burst read t 1 t 2 clk gpio0_fetch/ (driven by LSI53C825A) gpio1_master/ (driven by LSI53C825A) req/ (driven by LSI53C825A) pa r (driven by LSI53C825A- irdy/ (driven by LSI53C825A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad (driven by LSI53C825A- c_be/ (driven by LSI53C825A) t 3 gnt/ (driven by arbiter) frame/ (driven by LSI53C825A) t 2 t 2 addr; target-data) addr; target-data) be t 1 data in out in cmd cmd addr out addr out pci and external memory interface timing diagrams 6-29 figure 6.19 burst read (cont.) t 1 cmd t 2 be data in out in in out in be addr out clk gpio0_fetch/ (driven by LSI53C825A) gpio1_master/ (driven by LSI53C825A) req/ (driven by LSI53C825A) pa r (driven by LSI53C825A- irdy/ (driven by LSI53C825A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad (driven by LSI53C825A- c_be/ (driven by LSI53C825A) gnt/ (driven by arbiter) frame/ (driven by LSI53C825A) addr; target-data) addr; target-data) 6-30 speci?cations figure 6.20 burst write clk (driven by system) gpio0_ fetch/ pa r (driven by LSI53C825A) irdy/ (driven by LSI53C825A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad (driven by LSI53C825A) c_be/ (driven by LSI53C825A) t 3 frame/ (driven by LSI53C825A) (driven by LSI53C825A) t 3 t 3 t 3 t 3 t 3 t 3 req/ (driven by LSI53C825A) t 6 gpio1_ master/ (driven by LSI53C825A) t 9 t 10 addr out data out be addr out cmd cmd gnt/ (driven by arbiter) t 4 t 5 pci and external memory interface timing diagrams 6-31 figure 6.20 burst write (cont.) t 1 t 2 addr out be data out cmd t 1 t 2 be data out data out clk (driven by system) gpio0_ fetch/ pa r (driven by LSI53C825A) irdy/ (driven by LSI53C825A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad (driven by LSI53C825A) c_be/ (driven by LSI53C825A) gnt/ (driven by arbiter) frame/ (driven by LSI53C825A) (driven by LSI53C825A) req/ (driven by LSI53C825A) gpio1_ master/ (driven by LSI53C825A) 6-32 speci?cations 6.4.3 external memory timing figure 6.21 through figure 6.30 describe LSI53C825A external memory timing. figure 6.21 read cycle, normal/fast memory ( 3 64 kbytes), single byte access clk mad (addr driven by LSI53C825A; data driven by memory) mas2/ (driven by LSI53C825A) mas1/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) t 11 t 12 t 13 t 15f t 14f t 16f t 18 t 17 t 19 higher address 1. 2. 3. 1. middle address 2. lower address 3. valid read data mas0/ (driven by LSI53C825A) pci and external memory interface timing diagrams 6-33 figure 6.22 write cycle, normal/fast memory ( 3 64 kbytes), single byte access clk mad (driven by LSI53C825A) mas2/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) higher address lower address t 12 middle address t 11 t 13 t 21 t 22f t 20 t 23 t 24f t 25 t 26 mas1/ (driven by LSI53C825A) valid write data 6-34 speci?cations figure 6.23 read cycle, normal/fast memory ( 3 64 kbytes), multiple byte access mad (addr driven by LSI53C825A; mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) data driven by memory) clk (driven by system) pa r (driven by LSI53C825A- irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) ad (driven by LSI53C825A- c_be/ (driven by master) frame/ (driven by master) master-addr; data) master-addr; data) byte enable addr in cmd in lower address gpio2_mas2/ (driven by LSI53C825A) 0 2 4 6 8 101214 1 35 7 9111315 upper address middle address pci and external memory interface timing diagrams 6-35 figure 6.23 read cycle, normal/fast memory ( 3 64 kbytes), multiple byte access (cont.) mad (addr driven by LSI53C825A; mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) data driven by memory) clk (driven by system) pa r (driven by LSI53C825A- irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) ad (driven by LSI53C825A- c_be/ (driven by master) frame/ (driven by master) master-addr; data) master-addr; data) gpio2_mas2/ (driven by LSI53C825A) byte enable data in lower address data in 16 18 19 22 24 26 28 30 17 33 20 21 23 25 27 29 31 32 data out out 6-36 speci?cations figure 6.24 write cycle, normal/fast memory ( 3 64 kbytes), multiple byte access mad (driven by LSI53C825A) gpio2_mas2/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) 0 2 4 6 8 101214 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) ad (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) LSI53C825A-data) LSI53C825A-data) byte enable addr in cmd in upper address middle address lower address data in mas1/ (driven by LSI53C825A) 1 35 7 9111315 pci and external memory interface timing diagrams 6-37 figure 6.24 write cycle, normal/fast memory ( 3 64 kbytes), multiple byte access (cont.) in 16 18 19 22 24 26 28 30 17 33 mad (driven by LSI53C825A) gpio2_mas2/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C825A) stop/ (driven by LSI53C825A) devsel/ (driven by LSI53C825A) ad (driven by master-addr; c_be/ (driven by master) frame/ (driven by master) LSI53C825A-data) LSI53C825A-data) mas1/ (driven by LSI53C825A) lower address byte enable data in 20 21 23 25 27 29 31 32 data out data out 6-38 speci?cations figure 6.25 read cycle, slow memory ( 3 64 kbytes) t 14s t 18 t 19 t 17 t 11 t 12 t 13 t 15s t 16s clk mas2/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) mad (address driven by LSI53C825A; data driven by memory) higher address middle address lower address valid read data mas1/ (driven by LSI53C825A) pci and external memory interface timing diagrams 6-39 figure 6.26 write cycle, slow memory ( 3 64 kbytes) clk mad (driven by LSI53C825A) mas2/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) higher address t 11 t 12 t 13 t 24s t 25 t 20 t 23 t 22s t 26 t 21 1. 2. 1. middle address 2. lower address valid write data mas1/ (driven by LSI53C825A) 6-40 speci?cations figure 6.27 read cycle, normal/fast memory ( 3 64 kbytes) t 14f t 18 t 19 t 17 t 11 t 12 t 13 t 15f t 16f clk mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) mad (address driven by LSI53C825A; data driven by memory) lower address mas2/ (driven by LSI53C825A) higher address valid read data pci and external memory interface timing diagrams 6-41 figure 6.28 write cycle, normal/fast memory ( 3 64 kbytes) mad (driven by LSI53C825A) mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) higher address lower address t 12 valid write data t 11 t 13 t 24f t 25 t 26 mas2/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) t 21 t 22f t 20 t 23 clk 6-42 speci?cations figure 6.29 read cycle, slow memory ( 64 kbytes) mad (address driven by LSI53C825A; data driven by memory) mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) t 17 t 12 t 15s t 14s t 18 t 16s t 19 mas2/ (driven by LSI53C825A) clk higher address lower address valid read data t 13 t 11 pci and external memory interface timing diagrams 6-43 figure 6.30 write cycle, slow memory ( 64 kbytes) mad (driven by LSI53C825A) mas1/ (driven by LSI53C825A) mas0/ (driven by LSI53C825A) mce/ (driven by LSI53C825A) moe/ (driven by LSI53C825A) mwe/ (driven by LSI53C825A) t 11 t 12 t 13 t 24s t 25 t 20 t 23 t 22s t 26 t 21 mas2/ (driven by LSI53C825A) clk lower address higher address valid write data 6-44 speci?cations 6.5 pci and external memory interface timing table 6.19 lists the LSI53C825A pci and external memory interface timing data. table 6.19 LSI53C825A pci and external memory interface timing symbol parameter min max unit t 1 shared signal input setup time 7 C ns t 2 shared signal input hold time 0 C ns t 3 clk to shared signal output valid C 11 ns t 4 side signal input setup time 10 C ns t 5 side signal input hold time 0 C ns t 6 clk to side signal output valid C 12 ns t 7 clk high to fetch/ low C 20 ns t 8 clk high to fetch/ high C 20 ns t 9 clk high to master/ low C 20 ns t 10 clk high to master/ high C 20 ns t 11 address setup to mas/ high 25 C ns t 12 address hold from mas/ high 15 C ns t 13 mas/ pulse width 25 C ns t 14f mce/ low to data clocked in (fast memory) 160 C ns t 14s mce/ low to data clocked in (slow memory) 220 C ns t 15f address valid to data clocked in (fast memory) 205 C ns t 15s address valid to data clocked in (slow memory) 265 C ns t 16f moe/ low to data clocked in (fast memory) 100 C ns t 16s moe/ low to data clocked in (slow memory) 160 C ns t 17 data hold from address, moe/, mce/ change 0 C ns t 18 next address out from moe/, mce/ high 50 C ns t 19 data setup to clk high 5 C ns t 20 data setup to mwe/ low 30 C ns t 21 data hold from mwe/ high 20 C ns t 25 mce/ low to mwe/ low 25 C ns t 26 mwe/ high to mce/ high 25 C ns scsi timing diagrams 6-45 6.6 scsi timing diagrams table 6.20 through table 6.27 and figure 6.31 through figure 6.35 describe the LSI53C825A scsi timing. figure 6.31 initiator asynchronous send table 6.20 initiator asynchronous send symbol parameter min max unit t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sack/ asserted 55 C ns t 4 data hold from sreq/ deasserted 20 C ns sreq/ sack/ sd[15:0]/ sdp[1:0]/ t 1 t 2 t 3 t 4 n + 1 n valid n valid n + 1 n + 1 6-46 speci?cations figure 6.32 initiator asynchronous receive table 6.21 initiator asynchronous receive symbol parameter min max unit t 1 sack/ asserted from sreq/ asserted 5 C ns t 2 sack/ deasserted from sreq/ deasserted 5 C ns t 3 data setup to sreq/ asserted 0 C ns t 4 data hold from sack/ asserted 0 C ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 1 t 2 n + 1 valid n + 1 valid n n t 3 t 4 n n + 1 scsi timing diagrams 6-47 figure 6.33 target asynchronous send table 6.22 target asynchronous send symbol parameter min max unit t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sreq/ asserted 55 C ns t 4 data hold from sack/ asserted 20 C ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 3 t 2 t 1 valid n valid n + 1 n + 1 n t 4 n + 1 n 6-48 speci?cations figure 6.34 target asynchronous receive figure 6.35 initiator and target synchronous transfers table 6.23 target asynchronous receive symbol parameter min max unit t 1 sreq/ deasserted from sack/ asserted 5 C ns t 2 sreq/ asserted from sack/ deasserted 5 C ns t 3 data setup to sack/ asserted 0 C ns t 4 data hold from sreq/ deasserted 0 C ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ n n + 1 t 2 t 1 t 3 t 4 valid n valid n + 1 n + 1 n sreq/ or sack/ send data sd[15:0]/, sdp[1:0]/ receive data sd[15:0]/, sdp[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 n n + 1 valid n valid n + 1 valid n valid n + 1 scsi timing diagrams 6-49 table 6.24 scsi-1 transfers (se 5.0 mbytes) symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 90 C ns t 2 send sreq/ or sack/ deassertion pulse width 90 C ns t 1 receive sreq/ or sack/ assertion pulse width 90 C ns t 2 receive sreq/ or sack/ deassertion pulse width 90 C ns t 3 send data setup to sreq/ or sack/ asserted 55 C ns t 4 send data hold from sreq/ or sack/ asserted 100 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 45 C ns table 6.25 scsi-1 transfers (differential, 4.17 mbytes/s) symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 96 C ns t 2 send sreq/ or sack/ deassertion pulse width 96 C ns t 1 receive sreq/ or sack/ assertion pulse width 84 C ns t 2 receive sreq/ or sack/deassertion pulse width 84 C ns t 3 send data setup to sreq/ or sack/ asserted 65 C ns t 4 send data hold from sreq/ or sack/ asserted 110 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 45 C ns 6-50 speci?cations table 6.26 scsi-2 fast transfers (10.0 mbytes/s (8-bit transfers) or 20.0 mbytes/s (16-bit transfers), 40 mhz clock) symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 35 C ns t 2 send sreq/ or sack/ deassertion pulse width 35 C ns t 1 receive sreq/ or sack/ assertion pulse width 20 C ns t 2 receive sreq/ or sack/ deassertion pulse width 20 C ns t 3 send data setup to sreq/ or sack/ asserted 33 C ns t 4 send data hold from sreq/ or sack/ asserted 45 C ns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 10 C ns table 6.27 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes/s (16-bit transfers) 50 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 35 C ns t 2 send sreq/ or sack/ deassertion pulse width 35 C ns t 1 receive sreq/ or sack/ assertion pulse width 20 C ns t 2 receive sreq/ or sack/ deassertion pulse width 20 C ns t 3 send data setup to sreq/ or sack/ asserted 33 C ns t 4 send data hold from sreq/ or sack/ asserted 40 1 1. analysis of system con?guration is recommended due to reduced driver skew margin in differential systems. notes: transfer period bits (bits [7:5] in the scsi transfer (sxfer) register) are set to zero and the extra clock cycle of data setup bit (bit 7 in scsi control one (scntl1) ) is set. for fast scsi, set the tolerant enable bit (bit 7 in scsi test three (stest3) ). Cns t 5 receive data setup to sreq/ or sack/ asserted 0 C ns t 6 receive data hold from sreq/ or sack/ asserted 10 C ns scsi timing diagrams 6-51 this page intentionally left blank. 6-52 speci?cations 6.7 package drawings figure 6.36 is the mechanical drawing for the LSI53C825A. figure 6.36 LSI53C825A 160 pin pqfp (pf) mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code pf. package drawings 6-53 figure 6.36 LSI53C825A 160 pin pqfp (pf) mechanical drawing (cont.) impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code pf. 6-54 speci?cations LSI53C825A/825ae pci to scsi i/o processor a-1 appendix a register summary table a.1 lists the LSI53C825A con?guration registers by register name. table a.1 con?guration registers register name address read/write page base address one (memory) 0x14 read/write 4-9 base address zero (i/o) 0x10 read/write 4-9 bridge support extensions (pmcsr_bse) 0x46 read only 4-17 cache line size 0x0c read/write 4-8 capability id 0x40 read only 4-14 capability pointer 0x34 read only 4-12 class code 0x09 read only 4-7 command 0x04 read/write 4-3 data 0x47 read only 4-17 device id 0x02 read only 4-3 expansion rom base address 0x30 read/write 4-11 header type 0x0e read only 4-9 interrupt line 0x3c read/write 4-13 interrupt pin 0x3d read only 4-13 latency timer 0x0d read/write 4-8 max_lat 0x3f read only 4-14 min_gnt 0x3e read only 4-13 next item pointer 0x41 read only 4-15 a-2 register summary table a.2 lists the LSI53C825A register map by register name. power management capabilities 0x42 read only 4-15 power management control/status 0x44 read write 4-16 ram base address two (memory) scripts ram 0x18 read/write 4-10 revision id 0x08 read only 4-7 status 0x06 read/write 4-5 subsystem id (ssid) 0x2e read only 4-11 subsystem vendor id (ssvid) 0x2c read only 4-10 vendor id 0x00 read only 4-3 table a.1 con?guration registers (cont.) register name address read/write page table a.2 LSI53C825A register map register name address read/write page adder sum output (adder) 0x3cC0x3f (0xbcC0xbf) read only 4-71 chip test five (ctest5) 0x22 (0xa2) read/write 4-59 chip test four (ctest4) 0x21 (0xa1) read/write 4-57 chip test one (ctest1) 0x19 (0x99) read only 4-52 chip test six (ctest6) 0x23 (0xa3) read/write 4-61 chip test three (ctest3) 0x1b (0x9b) read/write 4-54 chip test two (ctest2) 0x1a (0x9a) read/write 4-53 chip test zero (ctest0) 0x18 (0x98) read/write 4-52 data structure address (dsa) 0x10C0x13 (0x90C0x93) read/write 4-48 dma byte counter (dbc) 0x24C0x26 (0xa4C0xa6) read/write 4-62 dma command (dcmd) 0x27 (0xa7) read/write 4-63 dma control (dcntl) 0x3b (0xbb) read/write 4-69 dma fifo (dfifo) 0x20 (0xa0) read/write 4-56 register summary a-3 dma interrupt enable (dien) 0x39 (0xb9) read/write 4-68 dma mode (dmode) 0x3b (0xbb) read/write 4-65 dma next address (dnad) 0x28C0x2b (0xa8C0xab) read/write 4-63 dma scripts pointer (dsp) 0x2cC0x2f (0xacC0xaf) read/write 4-64 dma scripts pointer save (dsps) 0x30C0x33 (0xb0C0xb3) read/write 4-64 dma status (dstat) 0x0c (0x8c) read only 4-40 general purpose (gpreg) 0x07 (0x87) read/write 4-35 general purpose pin control (gpcntl) 0x47 (0xc7) read/write 4-81 interrupt status (istat) 0x14 (0x94) read/write 4-48 memory access control (macntl) 0x46 (0xc6) read/write 4-80 response id one (respid1) 0x4b (0xcb) read/write 4-86 response id zero (respid0) 0x4a (0xca) read/write 4-86 scratch byte register (sbr) 0x3a (0xba) read/write 4-69 scratch register a (scratcha) 0x34C0x37 (0xb4C0xb7) read/write 4-65 scratch register b (scratchb) 0x5cC0x5f (0xdcC0xdf) read/write 4-95 scratch registers cCj (scratchcCscratchj) 0x60C0x7f (0xe0C0xff) read/write 4-95 scsi bus control lines (sbcl) 0x0b (0x8b) read only 4-39 scsi bus data lines (sbdl) 0x58C0x59 (0xd8C0xd9) read only 4-94 scsi chip id (scid) 0x04 (0x84) read/write 4-30 scsi control one (scntl1) 0x01 (0x81) read/write 4-23 scsi control three (scntl3) 0x03 (0x83) read/write 4-28 scsi control two (scntl2) 0x02 (0x82) read/write 4-26 scsi control zero (scntl0) 0x00 (0x80) read/write 4-20 scsi destination id (sdid) 0x06 (0x86) read/write 4-35 scsi first byte received (sfbr) 0x08 (0x88) read/write 4-37 table a.2 LSI53C825A register map (cont.) register name address read/write page a-4 register summary scsi input data latch (sidl) 0x50C0x51 (0xd0C0xd1) read only 4-93 scsi interrupt enable one (sien1) 0x41 (0xc1) read/write 4-73 scsi interrupt enable zero (sien0) 0x40 (0xc0) read/write 4-71 scsi interrupt status one (sist1) 0x43 (0xc3) read only 4-77 scsi interrupt status zero (sist0) 0x42 (0xc2) read only 4-74 scsi longitudinal parity (slpar) 0x44 (0xc4) read/write 4-78 scsi output control latch (socl) 0x09 (0x89) read/write 4-38 scsi output data latch (sodl) 0x54C0x55 (0xd4C0xd5) read/write 4-94 scsi selector id (ssid) 0x0a (0x09) read only 4-39 scsi status one (sstat1) 0x0e (0x8e) read only 4-44 scsi status two (sstat2) 0x0f (0x8f) read only 4-46 scsi status zero (sstat0) 0x0d (0x8d) read only 4-43 scsi test one (stest1) 0x4d (0xcd) read/write 4-88 scsi test three (stest3) 0x4f (0xcf) read/write 4-91 scsi test two (stest2) 0x4e (0xce) read/write 4-89 scsi test zero (stest0) 0x4c (0xcc) read only 4-87 scsi timer one (stime1) 0x49 (0xc9) read/write 4-84 scsi timer zero (stime0) 0x48 (0xc8) read/write 4-82 scsi transfer (sxfer) 0x05 (0x85) read/write 4-31 scsi wide residue (swide) 0x45 (0xc5) read/write 4-79 temporary (temp) 0x1cC0x1f (0x9cC0x9f) read/write 4-56 table a.2 LSI53C825A register map (cont.) register name address read/write page LSI53C825A/825ae pci to scsi i/o processor b-1 appendix b external memory interface diagram examples figure b.1 64 kbyte interface with 200 ns memory LSI53C825A 27c128 moe/ oe mce/ ce d0 8 mad[7:0] bus d7 q0 8 a[7:0] q7 6 a[13:8] 6 v ss mas0/ mas1/ 8 note: mad bus sense logic enabled for 16 kbytes of slow memory (200 ns device @ 33 mhz). hct374 d[7:0] mad3 4.7 k mad2 4.7 k mad1 4.7 k mad0 4.7 k ck 0e d0 d5 q0 q5 hct374 ck 0e b-2 external memory interface diagram examples figure b.2 64 kbyte interface with 150 ns memory LSI53C825A 27c512-15/ moe/ oe mce/ ce 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 v ss mas0/ mas1/ 8 note: mad bus sense logic enabled for 64 kbytes of fast memory (150 ns device @ 33 mhz). gpio4 mwe/ v pp control + 12 v v pp we optional - for flash memory only, not required for eeproms. 28f512-15/ socket d[7:0] mad3 4.7 k mad1 4.7 k d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e external memory interface diagram examples b-3 figure b.3 256 kbyte interface with 150 ns memory LSI53C825A 27c020-15/ moe/ oe mce/ ce 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 mas0/ mas1/ 8 note: mad bus sense logic enabled for 256 kbytes of fast memory (150 ns device @ 33 mhz). address latch for the two most signi?cant bits can be hct74, hct174, hct175, etc. gpio4 mwe/ v pp control + 12 v v pp we optional - for flash memory only, not required for eeproms. 28f020-15/ socket d[7:0] 2 2 a[17:16] v ss mad2 4.7 k mad1 4.7 k d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e d0 d1 q0 q1 hct374 ck 0e gpio2_mas2/ b-4 external memory interface diagram examples figure b.4 512 kbyte interface with 150 ns memory LSI53C825A moe/ 8 mad[7:0] bus 8 a[7:0] 8 a[15:8] 8 v ss mas0/ mas1/ 8 note: mad bus sense logic enabled for 512 kbytes of slow memory (150 ns device, additional time required for hct139 @ 33 mhz). gpio4 mwe/ v pp control + 12 v v pp optional - for flash memory only, not required for eeproms. d[7:0] mad0 4.7 k 3 mad2 4.7 k oe d0 a0 a16 oe d0 a0 a16 oe d0 a0 a16 oe d0 a0 a16 a b gb y0 y1 y2 y3 mce/ hct139 ce ce ce ce 27c010-15/28f010-15 sockets d0 d7 q0 q7 hct374 ck 0e d0 d7 q0 q7 hct374 ck 0e d0 d2 q0 q2 hct374 ck 0e gpio2_mas2/ a16 d7 d7 d7 d7 a17 a18 LSI53C825A/825ae pci to scsi i/o processor ix-1 index symbols (aap) 4-22 (abrt) 4-41 , 4-48 (ack) 4-38 , 4-39 (adb) 4-23 (adck) 4-59 (adder) 4-70 (aesp) 4-24 (aip) 4-44 (arb[1:0]) 4-20 (art) 4-86 (atn) 4-38 , 4-39 (aws) 4-89 (baro[31:0]) 4-9 , 4-10 (barz[31:0]) 4-9 (bbck) 4-59 (bdis) 4-57 (bf) 4-41 , 4-67 (bl[1:0]) 4-64 (bl2) 4-60 (bo[7:0]) 4-56 (bo[9:8]) 4-60 (bof) 4-66 (bse[7:0]) 4-17 (bsy) 4-38 , 4-39 (c_d) 4-38 , 4-40 , 4-45 (ccf[2:0]) 4-29 (chm) 4-26 (cid[7:0]) 4-14 (cio) 4-53 (clf) 4-55 (cls[7:0]) 4-8 (clse) 4-68 (cm) 4-53 (cmp) 4-71 , 4-74 (com) 4-70 (con) 4-24 , 4-50 (cp[7:0]) 4-12 (csf) 4-91 (ctest0) 4-52 (ctest1) 4-52 (ctest2) 4-53 (ctest3) 4-54 (ctest4) 4-57 (ctest5) 4-59 (ctest6) 4-60 (dack) 4-54 (data[7:0]) 4-17 (dbc) 4-61 (dcmd) 4-62 (dcntl) 4-68 (ddir) 4-53 , 4-60 (df[7:0]) 4-60 (dfe) 4-40 (dfifo) 4-56 (dfs) 4-59 (dhp) 4-24 (dien) 4-67 (dif) 4-88 (diff) 4-47 (diom) 4-65 (dip) 4-51 (dmode) 4-64 (dnad) 4-62 (dreq) 4-54 (dsa) 4-48 (dsi) 4-91 (dsp) 4-63 (dsps) 4-63 (dstat) 4-40 (enc[3:0]) 4-30 , 4-35 (enid[3:0]) 4-39 (epc) 4-22 (erba[31:0]) 4-11 (erl) 4-66 (ermp) 4-66 (ews) 4-29 (exc) 4-23 (ext) 4-89 (fbl[2:0]) 4-58 (fe) 4-80 (ff[3:0]) 4-44 (ff4) 4-47 (ffl[3:0]) 4-52 (flf) 4-54 (fm) 4-55 (fmt) 4-52 (gen) 4-73 , 4-76 (gen[3:0]) 4-84 (gensf) 4-83 (gpcntl) 4-80 (gpio[1:0]) 4-80 (gpio[4:0]) 4-35 (gpio[4:2]) 4-80 (gpreg) 4-35 (hsc) 4-90 (ht[7:0]) 4-9 (hth) 4-73 , 4-76 (hth[3:0]) 4-81 (hthba) 4-83 (hthsf) 4-84 (i/o) 4-38 , 4-40 , 4-45 ix-2 index (iarb) 4-25 (iid) 4-41 , 4-67 (il[7:0]) 4-13 (ilf) 4-43 (ilf1) 4-46 (intf) 4-50 (ip[7:0]) 4-13 (irqd) 4-69 (irqm) 4-69 (istat) 4-48 (ldsc) 4-47 (loa) 4-44 (low) 4-89 (lt[7:0]) 4-8 (m/a) 4-71 , 4-74 (macntl) 4-79 (man) 4-66 (masr) 4-59 (mdpe) 4-41 , 4-67 (me) 4-80 (mg[7:0]) 4-13 (ml[7:0]) 4-14 (mo[4:0]) 4-34 (mpee) 4-58 (msg) 4-38 , 4-40 , 4-45 (nip[7:0]) 4-15 (olf) 4-43 (olf1) 4-46 (orf) 4-43 (orf1) 4-46 (par) 4-72 , 4-75 (pfen) 4-68 (pff) 4-68 (r) 4-80 (req) 4-38 , 4-39 (respid0) 4-85 (rof) 4-88 (rre) 4-30 (rsl) 4-71 , 4-74 (rst) 4-24 , 4-44 , 4-72 , 4-75 (s16) 4-91 (sbcl) 4-39 (sbdl) 4-93 (sbr) 4-68 (sce) 4-88 (scf[2:0]) 4-28 (scid) 4-30 (sclk) 4-87 (scntl0) 4-20 (scntl1) 4-23 (scntl2) 4-26 (scntl3) 4-28 (scratcha) 4-64 (scratchb) 4-94 (scratchcCscratchr) 4-94 (sdid) 4-35 (sdp0) 4-44 (sdp0l) 4-45 (sdp1) 4-47 (sdu) 4-26 (sel) 4-38 , 4-39 , 4-71 , 4-74 (sem) 4-49 (sfbr) 4-37 (sge) 4-71 , 4-74 (sid[15:0]) 4-11 (sien0) 4-70 (sien1) 4-72 (sigp) 4-49 , 4-53 (sip) 4-50 (sir) 4-41 , 4-67 (siso) 4-87 (sist0) 4-73 (sist1) 4-76 (slb) 4-88 (slpar) 4-77 (slphben) 4-27 (slpmd) 4-27 (slt) 4-86 (socl) 4-38 (sodl) 4-93 (som) 4-87 (soz) 4-86 (spl1) 4-47 (sre) 4-30 (srst) 4-49 (srtch) 4-53 (srtm) 4-58 (ssaid[3:0]) 4-86 (ssi) 4-41 , 4-67 (ssid) 4-39 (ssm) 4-69 (sst) 4-25 (sstat0) 4-43 (sstat1) 4-44 (sstat2) 4-46 (start) 4-21 (std) 4-69 (stest0) 4-86 (stest1) 4-87 (stest2) 4-88 (stest3) 4-90 (stime0) 4-81 (stime1) 4-83 (sto) 4-73 , 4-76 (str) 4-90 (stw) 4-91 (swide) 4-78 (sxfer) 4-31 (szm) 4-89 (te) 4-90 (temp) 4-55 (teop) 4-54 (tp[2:0]) 4-31 (trg) 4-23 (ttm) 4-91 (typ[3:0]) 4-79 (udc) 4-72 , 4-75 (v[3:0]) 4-54 (val) 4-39 (vue0) 4-27 (vue1) 4-27 (watn) 4-22 (woa) 4-44 (wrie) 4-55 (wsr) 4-28 (wss) 4-27 (zmod) 4-57 (zsd) 4-57 numerics 16-bit system (s16) 4-91 3-state 3-4 index ix-3 a a[6:0] 5-26 abort operation (abrt) 4-48 aborted (abrt) 4-41 , 4-67 absolute maximum stress ratings 6-2 ac characteristics 6-11 active termination 2-29 adder sum output (adder) 4-70 address and data signals 3-7 always wide scsi (aws) 4-89 arbitration arbitration signals 3-9 in progress (aip) 4-44 mode bits 1 and 0 (arb[1:0]) 4-20 priority encoder test (art) 4-86 assert even scsi parity (force bad parity) (aesp) 4-24 satn/ on parity error (aap) 4-22 scsi ack/ signal (ack) 4-38 , 4-39 atn/ signal (atn) 4-38 , 4-39 bsy/ signal (bsy) 4-38 , 4-39 c_d/ signal (c_d) 4-38 , 4-40 data bus (adb) 4-23 i_o/ signal (i/o) 4-38 , 4-40 msg/ signal (msg) 4-38 , 4-40 req/ signal (req) 4-38 , 4-39 rst/ signal (rst) 4-24 sel/ signal (sel) 4-38 , 4-39 b base address register one (baro[31:0]) 4-9 one (bart[31:0]) 4-10 zero - i/o (barz[31:0]) 4-9 bidirectional 3-4 big and little endian support 2-19 block move instructions 5-6 bridge support extensions (bse[7:0]) 4-17 burst disable (bdis) 4-57 length (bl[1:0]) 4-64 length bit 2 (bl2) 4-60 opcode fetch enable (bof) 4-66 bus fault (bf) 4-41 , 4-67 byte count 5-41 empty in dma fifo (fmt) 4-52 full in dma fifo (ffl[3:0]) 4-52 offset counter (bo[7:0]) 4-56 c cache line size (cls[7:0]) 4-8 enable (clse) 4-68 call instruction 5-30 cap_id (cid[7:0]) 4-14 capabilities pointer (cp[7:0]) 4-12 carry test 5-34 chained block moves 2-42 sodl register 2-43 swide register 2-43 wide scsi receive bit 2-42 wide scsi send bit 2-42 chained mode (chm) 4-26 chip revision level (v[3:0]) 4-54 test five (ctest5) 4-59 test four (ctest4) 4-57 test one (ctest1) 4-52 test six (ctest6) 4-60 test three (ctest3) 4-54 test two (ctest2) 4-53 test zero (ctest0) 4-52 type (typ[3:0]) 4-79 clear dma fifo (clf) 4-55 clear instruction 5-16 , 5-19 clear scsi fifo (csf) 4-91 clock address incrementor (adck) 4-59 byte counter (bbck) 4-59 conversion factor (ccf[2:0]) 4-29 compare data 5-35 phase 5-35 configured as i/o (cio) 4-53 as memory (cm) 4-53 connected (con) 4-24 , 4-50 d data (data[7:0]) 4-17 acknowledge status (dack) 4-54 compare mask 5-36 compare value 5-36 request status (dreq) 4-54 structure address (dsa) 4-48 transfer direction (ddir) 4-53 data path 2-24 destination address 5-26 i/o-memory enable (diom) 4-65 differential mode diffsens 3-12 direction control pins 3-10 operation 2-28 diffsens mismatch (diff) 4-47 diffsens scsi signal 6-3 direct 5-21 disable halt on parity error or atn (target only) (dhp) 4-24 single initiator response (dsi) 4-91 disconnect instruction 5-15 dma byte counter (dbc) 4-61 command (dcmd) 4-62 control (dcntl) 4-68 direction (ddir) 4-60 fifo (df[7:0]) 4-60 (dfifo) 4-56 byte offset counter, bits [9:8] (bo[9:8]) 4-60 empty (dfe) 4-40 size (dfs) 4-59 interrupt enable (dien) 4-67 ix-4 index dma (cont.) interrupt pending (dip) 4-51 mode (dmode) 4-64 next address (dnad) 4-62 scripts pointer (dsp) 4-63 pointer save (dsps) 4-63 status (dstat) 4-40 dma core 2-11 dsa relative 5-41 dsps register 5-38 e enable parity checking (epc) 4-22 read line (erl) 4-66 multiple (ermp) 4-66 response to reselection (rre) 4-30 selection (sre) 4-30 wide scsi (ews) 4-29 encoded chip scsi id (enc[3:0]) 4-30 destination scsi id (enc[3:0]) 4-35 (enid[3:0]) 4-39 scsi destination id 5-22 error reporting signals 3-9 expansion rom base address 4-11 extend sreq/sack filtering (ext) 4-89 external clock 6-11 external memory interface 2-14 configuration 2-16 flash rom updates 2-14 memory sizes supported 2-16 multiple byte accesses 6-13 slow memory 2-16 system requirements 2-14 extra clock cycle of data setup (exc) 4-23 f fetch enable (fe) 4-80 pin mode (fm) 4-55 fifo byte control (fbl[2:0]) 4-58 flags (ff[3:0]) 4-44 flags, bit 4 (ff4) 4-47 first dword 5-6 , 5-14 , 5-24 , 5-29 , 5-41 flush dma fifo (flf) 4-54 full arbitration, selection/reselection 4-21 function complete (cmp) 4-71 , 4-74 g general purpose (gpreg) 4-35 i/o (gpio[4:0]) 4-35 pin control (gpcntl) 4-80 timer expired (gen) 4-73 , 4-76 timer period (gen[3:0]) 4-84 timer scale factor (gensf) 4-83 gpio enable (gpio[1:0]) 4-80 gpio enable (gpio[4:2]) 4-80 h halt scsi clock (hsc) 4-90 handshake-to-handshake timer bus activity enable (hthba) 4-83 timer expired (hth) 4-73 , 4-76 timer period (hth[3:0]) 4-81 timer scale factor (hthsf) 4-84 header type (ht[7:0]) 4-9 high impedance mode (szm) 4-89 high impedance mode (zmod) 4-57 hvd or se/lvd (dif) 4-88 i i/o instructions 5-14 illegal instruction detected (iid) 4-41 , 4-67 immediate arbitration (iarb) 4-25 data 5-26 indirect addressing 5-6 initiator mode 5-18 phase mismatch 4-74 input 3-4 instruction type 5-41 block move 5-6 i/o instruction 5-14 memory move 5-37 read/write instruction 5-24 transfer control instruction 5-29 instructions block move 5-6 inta, intb disable (irqd) 4-69 interface control signals 3-8 interrupt instruction 5-32 line 4-13 on the fly 5-35 on-the-fly (intf) 4-50 output 6-13 pin (ip[7:0]) 4-13 status (istat) 4-48 interrupt-on-the-fly instruction 5-33 interrupts 2-35 fatal vs. nonfatal interrupts 2-37 halting 2-40 masking 2-38 sample interrupt service routine 2-41 stacked interrupts 2-39 irq mode (irqm) 4-69 j jump address 5-36 index ix-5 jump (cont.) call a relative address 5-34 call an absolute address 5-34 if true/false 5-35 instruction 5-29 l last disconnect (ldsc) 4-47 latched scsi parity (sdp0l) 4-45 for sd[15:8] (spl1) 4-47 latency timer (lt[7:0]) 4-8 load/store 5-41 lost arbitration (loa) 4-44 lsi53c700 family compatibility (com) 4-70 m mad bus programming mad[3:1] 3-17 manual start mode (man) 4-66 master control for set or reset pulses (masr) 4-59 data parity error (mdpe) 4-41 , 4-67 enable (me) 4-80 parity error enable (mpee) 4-58 max scsi synchronous offset (mo[4:0]) 4-34 max_lat (ml[7:0]) 4-14 maximum stress ratings 6-2 memory i/o address/dsa offset 5-42 move instructions 5-36 memory access control (macntl) 4-79 min_gnt (mg[7:0]) 4-13 move to/from sfbr cycles 5-27 n next_item_ptr (nip[7:0]) 4-15 no flush 5-37 store instruction only 5-41 o opcode 5-9 , 5-14 , 5-26 , 5-29 operating conditions 6-2 operating registers general information 4-18 operator 5-26 p parity error (par) 4-75 pci and external memory interface timing diagrams 6-13 pci commands 2-2 pci configuration registers 4-1 base address one (memory) 4-9 base address zero (i/o) 4-9 class code 4-7 command 4-3 device id 4-3 expansion rom base address 4-11 header type 4-9 interrupt line 4-13 interrupt pin 4-13 latency timer 4-8 max_lat 4-14 min_gnt 4-13 revision id 4-7 status 4-5 vendor id 4-3 pci configuration space 2-1 pci i/o space 2-2 pci memory space 2-2 prefetch enable (pfen) 4-68 flush (pff) 4-68 r read modify-write cycles 5-26 write instructions 5-24 write system memory from scripts 5-38 read/write instructions 5-24 , 5-27 system memory from scripts 5-38 register address 5-41 address - a[6:0] 5-26 register addresses pci configuration registers 0x02 4-3 0x04 4-3 0x06 4-5 0x08 4-7 0x09 4-7 0x0d 4-8 0x0e 4-9 0x10 4-9 0x3d 4-13 0x3e 4-13 0x3f 4-14 relative 5-21 relative addressing mode 5-19 , 5-33 reselect instruction 5-15 reselected (rsl) 4-71 , 4-74 reserved 4-80 reset input 6-12 scsi offset (rof) 4-88 response id zero (respid0) 4-85 return instruction 5-32 s scratch byte register (sbr) 4-68 register a (scratcha) 4-64 register b (scratchb) 4-94 registers cCr (scratchcCscratchr) 4-94 scratcha/b operation (srtch) 4-53 scripts interrupt instruction received (sir) 4-41 , 4-67 scripts processor 2-11 performance 2-11 ix-6 index scsi atn condition - target mode (m/a) 4-71 bus control lines (sbcl) 4-39 bus data lines (sbdl) 4-93 c_d/ signal (c_d) 4-45 chip id (scid) 4-30 clock (sclk) 4-87 control enable (sce) 4-88 control one (scntl1) 4-23 control three (scntl3) 4-28 control two (scntl2) 4-26 control zero (scntl0) 4-20 core 2-10 data high impedance (zsd) 4-57 destination id (sdid) 4-35 differential mode 2-28 disconnect unexpected (sdu) 4-26 encoded destination id 5-22 fifo test read (str) 4-90 fifo test write (stw) 4-91 first byte received (sfbr) 4-37 gross error (sge) 4-71 , 4-74 i_o/ signal (i/o) 4-45 input data latch (sidl) 4-92 instructions i/o 5-14 read/write 5-24 interrupt enable one (sien1) 4-72 interrupt enable zero (sien0) 4-70 interrupt pending (sip) 4-50 interrupt status one (sist1) 4-76 interrupt status zero (sist0) 4-73 isolation mode (siso) 4-87 longitudinal parity (slpar) 4-77 loopback mode (slb) 4-88 low level mode (low) 4-89 msg/ signal (msg) 4-45 output control latch (socl) 4-38 output data latch (sodl) 4-93 parity error (par) 4-72 phase 5-12 , 5-33 phase mismatch - initiator mode 4-71 reset condition (rst) 4-72 rst/ received (rst) 4-75 rst/ signal (rst) 4-44 sdp0/ parity signal (sdp0) 4-44 sdp1/ parity signal (sdp1) 4-47 selected as id (ssaid[3:0]) 4-86 selector id (ssid) 4-39 signals 3-10 status one (sstat1) 4-44 status two (sstat2) 4-46 status zero (sstat0) 4-43 synchronous offset maximum (som) 4-87 synchronous offset zero (soz) 4-86 synchronous transfer period (tp[2:0]) 4-31 termination 2-29 test one (stest1) 4-87 test three (stest3) 4-90 test two (stest2) 4-88 test zero (stest0) 4-86 timer one (stime1) 4-83 timer zero (stime0) 4-81 tolerant technology 1-3 transfer (sxfer) 4-31 true end of process 4-54 valid (val) 4-39 wide residue (swide) 4-78 scsi bus interface 2-27 to 2-33 scsi core 2-10 scsi instructions block move 5-6 scsi scripts operation 5-2 sample instruction 5-3 scsi-1 transfers (differential 4.17 mbytes) 6-49 scsi-1 transfers (single-ended 5.0 mbytes) 6-49 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock 6-50 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 50 mhz clock 6-50 second dword 5-13 , 5-23 , 5-26 , 5-36 , 5-38 , 5-42 select instruction 5-18 with atn/ 5-22 with satn/ on a start sequence (watn) 4-22 selected (sel) 4-71 , 4-74 selection or reselection time-out (sto) 4-73 , 4-76 selection response logic test (slt) 4-86 semaphore (sem) 4-49 set instruction 5-16 , 5-19 set/clear carry 5-22 sack/ 5-23 shadow register test mode (srtm) 4-58 sidl least significant byte full (ilf) 4-43 most significant byte full (ilf1) 4-46 signal process (sigp) 4-49 , 4-53 signals address and data signals 3-7 arbitration signals 3-9 error reporting signals 3-9 interface control signals 3-8 scsi signals 3-10 simple arbitration 4-20 single step interrupt (ssi) 4-41 , 4-67 step mode (ssm) 4-69 single-ended operation 2-27 slpar high byte enable (slphben) 4-27 slpar mode (slpmd) 4-27 sodl least significant byte full (olf) 4-43 most significant byte full (olf1) 4-46 sodr least significant byte full (orf) 4-43 most significant byte full (orf1) 4-46 software reset (srst) 4-49 source i/o-memory enable (siom) 4-65 stacked interrupts 2-39 start address 5-13 , 5-23 dma operation (std) 4-69 scsi transfer (sst) 4-25 sequence (start) 4-21 storage device management system (sdms) 2-12 stress ratings 6-2 subsystem id (sid[15:0]) 4-11 subsystem vendor id (svid[15:0]) 4-10 index ix-7 synchronous clock conversion factor (scf[2:0]) 4-28 synchronous data transfer rates 2-33 t table indirect 5-21 mode 5-20 table relative 5-21 target mode 5-9 , 5-15 satn/ active (m/a) 4-74 mode (trg) 4-23 timing 6-15 target asynchronous receive 6-48 target asynchronous send 6-47 temp register 5-38 temporary (temp) 4-55 termination 2-29 third dword 5-38 timer test mode (ttm) 4-91 tolerant 6-7 enable (te) 4-90 technology electrical characteristics 6-7 tolerant technology 1-3 benefits 1-4 totem pole output 3-4 transfer control instructions 5-29 count 5-38 counter 5-12 transfer rate synchronous 2-33 u unexpected disconnect (udc) 4-72 , 4-75 use data8/sfbr 5-26 v vendor unique enhancement, bit 1 (vue1) 4-27 unique enhancements, bit 0 (vue0) 4-27 w wait disconnect instruction 5-18 for valid phase 5-36 reselect instruction 5-19 select instruction 5-16 wide scsi chained block moves 2-42 receive (wsr) 4-28 send (wss) 4-27 won arbitration (woa) 4-44 write read instructions 5-24 read system memory from scripts 5-38 write and invalidate enable (wrie) 4-55 ix-8 index LSI53C825A/825ae pci to scsi i/o processor customer feedback we would appreciate your feedback on this document. please copy the following page, add your comments, and fax it to us at the number shown. if appropriate, please also fax copies of any marked-up pages from this document. impor tant: please include your name, phone number, fax number, and company address so that we may contact you directly for clari?cation or additional information. thank you for your help in improving the quality of our documents. customer feedback readers comments fax your comments to: lsi logic corporation technical publications m/s e-198 fax: 408.433.4333 please tell us how you rate this document: LSI53C825A/825ae pci to scsi i/o processor technical manual. place a check mark in the appropriate blank for each category. what could we do to improve this document? if you found errors in this document, please specify the error and page number. if appropriate, please fax a marked-up copy of the page(s). please complete the information below so that we may contact you directly for clari?cation or additional information. excellent good average fair poor completeness of information ____ ____ ____ ____ ____ clarity of information ____ ____ ____ ____ ____ ease of ?nding information ____ ____ ____ ____ ____ technical content ____ ____ ____ ____ ____ usefulness of examples and illustrations ____ ____ ____ ____ ____ overall manual ____ ____ ____ ____ ____ name date telephone title company name street city, state, zip department mail stop fax u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for habs) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arkansas w. e. tel: 972.235.9953 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 tempe i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 california agoura hills b. m. tel: 818.865.0266 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 tampa w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5575 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlingtonr i. e. tel: 781.270.9400 marlborough b. m. tel: 508.480.9099 woburn b. m. tel: 781.933.9010 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 609.222.9566 pine brook w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119 u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tulsa a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beavertonr b. m. tel: 503.524.0787 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 philadelphia a. e. tel: 800.526.4812 b. m. tel: 215.741.4080 w. e. tel: 800.871.9953 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 washington kirkland i. e. tel: 425.820.8100 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953 direct sales representatives by state (component and boards) e. a. earle associates e. l. electrodyne - ut grp group 2000 i. s. in?nity sales, inc. ion ion associates, inc. r. a. rathsburg associ- ates, inc. sgy synergy associates, inc. arizona tempe e. a. tel: 480.921.3305 california calabasas i. s. tel: 818.880.6480 irvine i. s. tel: 714.833.0300 san diego e. a. tel: 619.278.5441 illinois elmhurst r. a. tel: 630.516.8400 indiana cicero r. a. tel: 317.984.8608 ligonier r. a. tel: 219.894.3184 plain?eld r. a. tel: 317.838.0360 massachusetts burlington sgy tel: 781.238.0870 michigan byron center r. a. tel: 616.554.1460 good rich r. a. tel: 810.636.6060 novi r. a. tel: 810.615.4000 north carolina cary grp tel: 919.481.1530 ohio columbus r. a. tel: 614.457.2242 dayton r. a. tel: 513.291.4001 independence r. a. tel: 216.447.8825 pennsylvania somerset r. a. tel: 814.445.6976 texas austin ion tel: 512.794.9006 arlington ion tel: 817.695.8000 houston ion tel: 281.376.2000 utah salt lake city e. l. tel: 801.264.8050 wisconsin muskego r. a. tel: 414.679.8250 saukville r. a. tel: 414.268.1152 sales of?ces and design resource centers lsi logic corporation corporate headquarters tel: 408.433.8000 fax: 408.433.8989 north america california costa mesa - mint technology tel: 949.752.6468 fax: 949.752.6868 irvine tel: 949.809.4600 fax: 949.809.4444 pleasanton design center tel: 925.730.8800 fax: 925.730.8700 san diego tel: 858.467.6981 fax: 858.496.0548 silicon valley tel: 408.433.8000 fax: 408.954.3353 wireless design center tel: 858.350.5560 fax: 858.350.0171 colorado boulder tel: 303.447.3800 fax: 303.541.0641 colorado springs tel: 719.533.7000 fax: 719.533.7020 fort collins tel: 970.223.5100 fax: 970.206.5549 florida boca raton tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green tel: 270.793.0010 fax: 270.793.0040 maryland bethesda tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis tel: 612.921.8300 fax: 612.921.8399 new jersey red bank tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology tel: 609.489.5530 fax: 609.489.5531 new york fairport tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh tel: 919.785.4520 fax: 919.783.8909 oregon beaverton tel: 503.645.0589 fax: 503.645.6612 texas austin tel: 512.388.7294 fax: 512.388.4171 plano tel: 972.244.5000 fax: 972.244.5001 houston tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milano lsi logic s.p.a. tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka tel: 81.6.947.5281 fax: 81.6.947.5287 korea seoul lsi logic corporation of korea ltd tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd tel: 65.334.9061 fax: 65.334.4749 tel: 65.835.5040 fax: 65.732.5047 sweden stockholm lsi logic ab tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan taipei lsi logic asia, inc. taiwan branch tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd tel: 44.1344.426544 fax: 44.1344.481039 sales of?ces with design resource centers international distributors australia new south wales reptechnic pty ltd tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. tel: 86.10.6804.2534 fax: 86.10.6804.2521 france rungis cedex azzurri technology france tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd tel: 852.2428.0008 fax: 852.2401.2105 eastele tel: 852.2798.8860 fax: 852.2305.0640 india bangalore spike technologies india private ltd tel: 91.80.664.5530 fax: 91.80.664.9748 israel tel aviv eastronics ltd tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo global electronics corporation tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 yokohama-city macnica corporation tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag tel: 41.32.3743232 fax: 41.32.3743233 taiwan taipei avnet-mercuries corporation, ltd tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd tel: 886.2.2721.9533 fax: 886.2.2773.3756 serial semiconductor corporation, ltd tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd tel: 44.1628.826826 fax: 44.1628.829730 swindon ebv elektronik tel: 44.1793.849933 fax: 44.1793.859555 sales of?ces with design resource centers |
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